MODIFIED PROFILE GATE STRUCTURE FOR SEMICONDUCTOR DEVICE AND METHODS OF FORMING THEREOF

• US 20120049247A1
• Filed: 08/31/2010
• Published: 03/01/2012
• Est. Priority Date: 08/31/2010
• Status: Active Grant

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Inventors: Lee, Da-Yuan, Hsu, Kuang-Yuan, Yeh, Matt, Huang, Yi-Chen, Hsu, Fan-Yi, Ouyang, Hui, Huang, Ming-Jie, Liao, Shin Hsien
• Granted Patent: US 8,329,546 B2
• Time in Patent Office: Days
• US Class Current: 257/288
• CPC Class Codes: H01L 21/28114 characterised by the sectional shape, e.g. T, inverted-T
• CPC Class Codes: H01L 29/42376 characterised by the length or the sectional shape
• CPC Class Codes: H01L 29/495 the conductor material next to the insulator being a simple metal, e.g. W, Mo H01L29/4908, H01L29/4983 take precedence
• CPC Class Codes: H01L 29/4966 the conductor material next to the insulator being a composite material, e.g. organic material, TiN, MoSi2 H01L29/4908, H01L29/4983 take precedence
• CPC Class Codes: H01L 29/513 the variation being perpendicular to the channel plane
• CPC Class Codes: H01L 29/517 the insulating material comprising a metallic compound, e.g. metal oxide, metal silicate H01L29/518 takes precedence
• CPC Class Codes: H01L 29/6653 using the removal of at least part of spacer, e.g. disposable spacer
• CPC Class Codes: H01L 29/66545 using a dummy, i.e. replacement gate in a process wherein at least a part of the final gate is self aligned to the dummy gate
• CPC Class Codes: H01L 29/6656 using multiple spacer layers, e.g. multiple sidewall spacers

Abstract

A method of fabricating a semiconductor device is illustrated. A modified profile opening is formed on a substrate. The modified profile opening includes a first width proximate a surface of the substrate and a second width opposing the substrate. The second width is greater than the first width. A metal gate electrode is formed by filling the modified profile opening with a conductive material. A semiconductor device is also described, the device having a metal gate structure with a first width and a second, differing, width.

Claims

1. A method of fabricating a semiconductor device, comprising:

providing a substrate;

forming a modified profile opening on the substrate, wherein the modified profile opening includes a first width proximate a surface of the substrate and a second width opposing the substrate, the second width being greater than the first width; and

forming a metal gate electrode, wherein the forming the metal gate electrode includes filling the modified profile opening with a conductive material.

2. The method of claim 1, wherein the modified profile opening includes a first portion have arcuate sidewalls.

3. The method of claim 2, wherein the second width is disposed in the first portion.

4. The method of claim 1, further comprising:

forming a dummy gate structure on the substrate, and wherein the forming the modified profile opening includes removing the dummy gate structure from the substrate.

5. The method of claim 1, wherein the forming the modified profile opening includes:

performing a first etch process, wherein the first etch process removes a portion of a spacer element; and

performing a second etch process, following the first etch process, wherein the second etch process removes a dummy gate electrode.

6. The method of claim 5, wherein the first etch process removes a portion of a contact etch stop layer.

7. The method of claim 1, further comprising:

forming a high-k gate dielectric layer in the modified profile opening prior to forming the metal gate electrode.

8. The method of claim 1, further comprising:

forming a dummy gate structure on the substrate, wherein the dummy gate structure includes;

forming a first layer of a dummy gate electrode;

forming an intermediate layer on the first layer; and

forming a second layer of the dummy gate electrode on the intermediate layer.

9. The method of claim 8, further comprising:

forming a first spacer element abutting the dummy gate structure, wherein the first spacer element and the intermediate layer have substantially the same composition.

10. The method of claim 9, further comprising:

forming a second spacer element adjacent the first spacer element, wherein the second spacer element has a different composition that the first spacer element.

11. A method, comprising:

providing a semiconductor substrate;

forming a dummy gate structure on the semiconductor substrate;

thereafter removing the dummy gate structure, wherein the removing the dummy gate structure forms a modified profile opening on the substrate, wherein the modified profile opening has a first width and a second width different from the first width; and

forming a metal gate electrode in the modified profile opening.

12. The method of claim 11, further comprising:

forming a first spacer element and a second spacer element adjacent the dummy gate structure, and wherein the forming the dummy gate structure includes;

forming a first layer of a dummy gate electrode;

forming an intermediate layer on the first layer; and

forming a second layer of the dummy gate electrode on the intermediate layer, and wherein the first spacer element and the intermediate layer have substantially the same composition.

13. The method of claim 12, wherein the removing the dummy gate structure includes:

removing the second layer of the dummy gate electrode;

thereafter, removing the intermediate layer of the dummy gate electrode and a portion of the first spacer element; and

thereafter, removing the first layer of the dummy gate electrode.

14. The method of claim 12, wherein the intermediate layer is selected from the group consisting of silicon oxide, silicon nitride, silicon oxynitride, silicon carbide, fluoride-doped silicate glass (FSG), a low k dielectric material, and combinations thereof.

15. The method of claim 11, further comprising:

forming spacer elements adjacent the dummy gate structure;

forming an etch stop layer on the spacer elements; and

etching the spacer elements and etch stop layer to provide a first opening of the first width prior to removing the dummy gate structure, wherein the removing the dummy gate structure provides a second opening of the second width, wherein the second width is less than the first width, and wherein the first and second opening are continual.

16. The method of claim 11, wherein the first width is greater than the second width.

17. A semiconductor device, comprising:

a semiconductor substrate having a first surface; and

a metal gate structure disposed on the first surface of the semiconductor substrate, wherein the metal gate structure includes a first width and a second width greater than the first width, wherein the first width is proximate the first surface.

18. The device of claim 17, wherein the metal gate structure includes a first portion having arcuate sidewalls and a second portion having sidewalls substantially perpendicular to the first surface.

19. The device of claim 17, wherein the metal gate structure includes a first portion abutting a first spacer element and a second portion abutting a second spacer element, wherein the first portion has the first width and the second portion has the second width.

20. The device of claim 19, wherein the first spacer element has a different composition than the second spacer element.