SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF

• US 20120049283A1
• Filed: 08/22/2011
• Published: 03/01/2012
• Est. Priority Date: 08/26/2010
• Status: Active Grant

• Current Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Original Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Inventors: MIYAIRI, Hidekazu, MIZOGUCHI, Takafumi
• Granted Patent: US 8,735,231 B2
• Time in Patent Office: Days
• US Class Current: 257/347
• CPC Class Codes: H01L 21/283 Deposition of conductive or insulating materials for electrodes conducting electric current
• CPC Class Codes: H01L 21/707 of thin-film circuits or parts thereof
• CPC Class Codes: H01L 21/84 the substrate being other than a semiconductor body, e.g. being an insulating body
• CPC Class Codes: H01L 29/458 for thin film silicon, e.g. source or drain electrode
• CPC Class Codes: H01L 29/6675 Amorphous silicon or polysilicon transistors
• CPC Class Codes: H01L 29/78606 with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device H01L29/78642, H01L29/78645 take precedence
• CPC Class Codes: H01L 29/78609 for preventing leakage current H01L29/78618 takes precedence
• CPC Class Codes: H01L 29/78618 characterised by the drain or the source properties, e.g. the doping structure, the composition, the sectional shape or the contact structure silicide contacts, electrodes in general H01L29/458
• CPC Class Codes: H01L 29/78645 with multiple gate
• CPC Class Codes: H01L 29/78648 arranged on opposing sides of the channel
• CPC Class Codes: H01L 29/78672 Polycrystalline or microcrystalline silicon transistor
• CPC Class Codes: H01L 29/78696 characterised by the structure of the channel, e.g. multichannel, transverse or longitudinal shape, length or width, doping structure, or the overlap or alignment between the channel and the gate, the source or the drain, or the contacting structure of the channel H01L29/78612 takes precedence; transistors having a drain offset region or a lightly doped drain [LDD] H01L29/78621

Abstract

A dual-gate transistor including: a first insulating layer provided to cover a first conductive layer; a first semiconductor layer over the first insulating layer; second semiconductor layers over the first semiconductor layer, the second semiconductor layers are spaced from each other to expose the first semiconductor layer; impurity semiconductor layers over the second semiconductor layers; second conductive layers over the impurity semiconductor layers; second insulating layers over the second conductive layers; a third insulating layer to cover the first semiconductor layer, the second semiconductor layers, the impurity semiconductor layers, the second conductive layers, and the second insulating layers; and a third conductive layer at least over the third insulating layer, and in the dual-gate transistor including the first to third insulating layers with openings, the first insulating layer is substantially equal in thickness to the second insulating layer.

Claims

1. A semiconductor device comprising:

a first insulating layer provided to cover a first conductive layer;

a first semiconductor layer provided over the first insulating layer;

a pair of second semiconductor layers provided over the first semiconductor layer, the pair of second semiconductor layers being spaced from each other;

impurity semiconductor layers provided over the pair of second semiconductor layers;

second conductive layers provided over the impurity semiconductor layers so as to be in contact with the impurity semiconductor layers;

second insulating layers provided over the second conductive layers;

a third insulating layer provided over the first semiconductor layer, the pair of second semiconductor layers, the impurity semiconductor layers and the second insulating layers; and

a third conductive layer provided at least over the third insulating layer,

wherein a first opening portion is provided in the first insulating layer and the third insulating layer,

wherein a second opening portion is provided in one of the second insulating layers and the third insulating layer, and

wherein a thickness of the first insulating layer is substantially equal to a thickness of the second insulating layers.

3. A semiconductor device according to claim 1,

wherein the third insulating layer is thinner than the first insulating layer and than the second insulating layers.

5. A semiconductor device according to claim 1,

wherein the third conductive layer is connected to the first conductive layer via the first opening portion and the second conductive layers via the second opening portion.

2. A semiconductor device comprising:

a first insulating layer provided to cover a first conductive layer;

a first semiconductor layer provided over the first insulating layer;

a pair of second semiconductor layers provided over the first semiconductor layer, the pair of second semiconductor layers being spaced from each other;

impurity semiconductor layers provided over the pair of second semiconductor layers;

second conductive layers provided over the impurity semiconductor layers so as to be in contact with the impurity semiconductor layers;

second insulating layers provided over the second conductive layers;

a third insulating layer provided over the first semiconductor layer, the pair of second semiconductor layers, the impurity semiconductor layers and the second insulating layers; and

a third conductive layer provided at least over the third insulating layer,

wherein a first opening portion is provided in the first insulating layer and the third insulating layer,

wherein a second opening portion is provided in one of the second insulating layers and the third insulating layer, and

wherein a depth of the first opening portion is substantially equal to a depth of the second opening portion.

4. A semiconductor device according to claim 2,

wherein the third insulating layer is thinner than the first insulating layer and than the second insulating layers.

6. A semiconductor device according to claim 2,

wherein the third conductive layer is connected to the first conductive layer via the first opening portion and the second conductive layers via the second opening portion.

7. A method for manufacturing a semiconductor device comprising the steps of:

forming a first insulating layer over a first conductive layer;

forming a first semiconductor layer over the first insulating layer;

forming a second semiconductor layer over the first semiconductor layer;

forming an impurity semiconductor layer over the second semiconductor layer;

etching the impurity semiconductor layer, the second semiconductor layer and the first semiconductor layer with a first predetermined mask;

forming a second conductive layer over the impurity semiconductor layer;

forming a second insulating layer over the second conductive layer;

etching the second insulating layer and the second conductive layer with a second predetermined mask to form a pair of second insulating layers and a pair of second conducive layers;

etching the impurity semiconductor layer and the second semiconductor layer to form a pair of impurity semiconductor layers and a pair of second semiconductor layers so as to expose the first semiconductor layer between the pair of second semiconductor layers;

forming a third insulating layer at least over the pair of second insulating layers, the first semiconductor layer and the first insulating layer;

forming a first opening portion in the third insulating layer and the first insulating layer; and

forming a second opening portion in the third insulating layer and one of the pair of second insulating layers; and

forming a third conductive layer over the third insulating layer,

wherein a thickness of the first insulating layer is substantially equal to a thickness of the pair of second insulating layers.

9. The method for manufacturing a semiconductor device according to claim 7, wherein the second insulating layer and the second conductive layer are etched with a same etching step.

11. The method for manufacturing a semiconductor device according to claim 7,

wherein a thickness of the first insulating layer is 250 nm or more and 450 nm or less, and

wherein a thickness of the third insulating layer is 60 nm or more and less than 250 nm.

8. A method for manufacturing a semiconductor device comprising the steps of:

forming a first insulating layer over a first conductive layer;

forming a first semiconductor layer over the first insulating layer;

forming a second semiconductor layer over the first semiconductor layer;

forming an impurity semiconductor layer over the second semiconductor layer;

etching the impurity semiconductor layer, the second semiconductor layer and the first semiconductor layer with a first predetermined mask;

forming a second conductive layer over the impurity semiconductor layer;

forming a second insulating layer over the second conductive layer;

etching the second insulating layer and the second conductive layer with a second predetermined mask to form a pair of second insulating layers and a pair of second conducive layers;

etching the impurity semiconductor layer and the second semiconductor layer to form a pair of impurity semiconductor layers and a pair of second semiconductor layers so as to expose the first semiconductor layer between the pair of second semiconductor layers;

forming a third insulating layer at least over the pair of second insulating layers, the first semiconductor layer and the first insulating layer;

forming a first opening portion in the third insulating layer and the first insulating layer; and

forming a second opening portion in the third insulating layer and one of the pair of second insulating layers; and

forming a third conductive layer over the third insulating layer,

wherein a depth of the first opening portion is substantially equal to a depth of the second opening portion.

10. The method for manufacturing a semiconductor device according to claim 8,

wherein the second insulating layer and the second conductive layer are etched with a same etching step.

12. The method for manufacturing a semiconductor device according to claim 8,

wherein a thickness of the first insulating layer is 250 nm or more and 450 nm or less, and

wherein a thickness of the third insulating layer is 60 nm or more and less than 250 nm.