COMPOSITE WAFER SEMICONDUCTOR

• US 20120049299A1
• Filed: 08/27/2010
• Published: 03/01/2012
• Est. Priority Date: 08/27/2010
• Status: Active Grant

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Inventors: Chou, Bruce C.S.
• Granted Patent: US 8,507,358 B2
• Time in Patent Office: Days
• US Class Current: 257/417
• CPC Class Codes: B81B 2201/025 Inertial sensors not provided for in B81B2201/0235 - B81B2201/0242
• CPC Class Codes: B81B 7/0032 Packages or encapsulation processes for packaging MEMS B81C1/00261; packaging of smart-MEMS B81C1/0023
• CPC Class Codes: B81C 1/00246 Monolithic integration, i.e. micromechanical structure and electronic processing unit are integrated on the same substrate
• CPC Class Codes: B81C 2203/0109 Bonding an individual cap on the substrate
• CPC Class Codes: B81C 2203/0714 Forming the micromechanical structure with a CMOS process
• CPC Class Codes: H01L 2224/83805 involving forming a eutectic alloy at the bonding interface

Abstract

A composite wafer semiconductor device includes a first wafer and a second wafer. The first wafer has a first side and a second side, and the second side is substantially opposite the first side. The composite wafer semiconductor device also includes an isolation set is formed on the first side of the first wafer and a free space is etched in the isolation set. The second wafer is bonded to the isolation set. A floating structure, such as an inertia sensing device, is formed in the second wafer over the free space. In an embodiment, a surface mount pad is formed on the second side of the first wafer. Then, the floating structure is electrically coupled to the surface mount pad using a through silicon via (TSV) conductor.

Claims

1. A method of forming a composite wafer semiconductor, the method comprising:

providing a first wafer, the first wafer having a first side and a second side, the second side being substantially opposite the first side;

providing a second wafer;

forming an isolation set on the first side of the first wafer;

etching the isolation set to create a free space in the isolation set;

bonding the second wafer to the isolation set;

forming a floating structure in the second wafer over the free space;

forming a surface mount pad on the second side of the first wafer; and

electrically coupling the floating structure to the surface mount pad using a through silicon via (TSV) conductor.

2. The method of claim 1, providing the first wafer as a semiconductive material and providing the second wafer as a conductive material.

3. The method of claim 1, further comprising:

performing a chemical-mechanical polishing (CMP) process to surfaces to be bonded before performing the bonding.

4. The method of claim 1, further comprising:

forming an integrated circuit (IC) in the first wafer.

5. The method of claim 1, wherein form the floating structure in the second wafer includes forming the floating structure as an inertia sensing device.

6. The method of claim 1, further comprising:

providing a third wafer and bonding the third wafer to the second wafer, thereby hermetically sealing the floating structure.

7. The method of claim 1, further comprising:

providing a third wafer and bonding the third wafer to the first wafer, thereby hermetically sealing the floating structure.

8. The method of claim 1, further comprising:

supporting the floating structure using a support spring.

10. The method of claim 8, providing the first wafer as a semiconductive material and providing the second wafer as a conductive material.

11. The method of claim 8, performing the bonding of the second wafer to the second isolation set below approximately 500 C.

12. The method of claim 8, further comprising:

forming an integrated circuit (IC) in the first wafer.

13. The method of claim 8, electrically coupling a portion of the second conductor layer to a portion of the first conductor layer.

14. The method of claim 8, further comprising;

configuring a portion of the backside via conductor as a surface mount technology (SMT) pad.

15. The method of claim 8, further comprising:

forming an additional SMT pad on the back side isolation layer and electrically coupling the additional SMT pad to the IC.

17. The device of claim 15, wherein the first wafer comprises a semiconductive material, and wherein the second wafer comprises a conductive material.

18. The device of claim 15, wherein the second wafer is bonded to the second isolation set below approximately 500 C.

19. The device of claim 15, further comprising:

an integrated circuit (IC) formed in the first wafer.

20. The device of claim 15, wherein a portion of the second conductor layer electrically couples to a portion of the first conductor layer.

21. The device of claim 15, wherein a portion of the backside via conductor is configured as a surface mount technology (SMT) pad.

9. A method of forming a composite wafer semiconductor, the method comprising:

providing a first wafer and a second wafer;

forming a patterned first conductor layer and a first isolation set on a first side of the first wafer;

forming a patterned second conductor layer and a second isolation set on the first isolation set;

etching the second isolation set to create a free space in the second isolation set over a portion of the first isolation set;

bonding the second wafer to the second isolation set;

forming a microelectromechanical system (MEMS) device in the second wafer over the free space;

forming a first via conductor through the second wafer and through a portion of the second isolation set to the second conductor layer;

forming a backside via from a second side of the first wafer to the first conductor layer;

forming a backside isolation layer on the second side of the first wafer; and

forming a backside via conductor in the backside via.

16. A composite wafer semiconductor device comprising:

a first wafer;

a patterned first conductor layer and a first isolation set formed on a first side of the first wafer;

a patterned second conductor layer and a second isolation set formed on the first isolation set;

a free space etched in the second isolation set over a portion of the first isolation set;

a second wafer bonded to the second isolation set;

a microelectromechanical system (MEMS) device formed in the second wafer over the free space;

a first via conductor formed through the second wafer and through a portion of the second isolation set to the second conductor layer;

a backside via formed from a second side of the first wafer to the first conductor layer;

a backside isolation layer formed on the second side of the first wafer; and

a backside via conductor formed in the backside via.