MANUFACTURING FIXTURE FOR A RAMP-STACK CHIP PACKAGE

• US 20120049376A1
• Filed: 09/01/2010
• Published: 03/01/2012
• Est. Priority Date: 09/01/2010
• Status: Active Grant

• Current Assignee: Oracle International Corporation (Oracle Corporation)
• Original Assignee: Oracle International Corporation (Oracle Corporation)
• Inventors: Drost, Robert J., Douglas, David C., Harada, John A.
• Granted Patent: US 8,373,280 B2
• Time in Patent Office: Days
• US Class Current: 257/773
• CPC Class Codes: H01L 2223/54426 for alignment
• CPC Class Codes: H01L 2224/0401 Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
• CPC Class Codes: H01L 2224/06155 Covering only the peripheral area of the surface to be connected, i.e. peripheral arrangements
• CPC Class Codes: H01L 2224/131 with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
• CPC Class Codes: H01L 2224/16145 the bodies being stacked
• CPC Class Codes: H01L 2224/16265 the item being a discrete passive component
• CPC Class Codes: H01L 2224/2919 with a principal constituent of the material being a polymer, e.g. polyester, phenolic based polymer, epoxy
• CPC Class Codes: H01L 2224/29193 with a principal constituent of the material being a solid not provided for in groups H01L2224/291 - H01L2224/29191, e.g. allotropes of carbon, fullerene, graphite, carbon-nanotubes, diamond
• CPC Class Codes: H01L 2224/32145 the bodies being stacked
• CPC Class Codes: H01L 2224/73203 Bump and layer connectors
• CPC Class Codes: H01L 2224/73253 Bump and layer connectors
• CPC Class Codes: H01L 2224/81815 Reflow soldering
• CPC Class Codes: H01L 2224/92143 the second connecting process involving a bump connector
• CPC Class Codes: H01L 2225/06513 Bump or bump-like direct electrical connections between devices, e.g. flip-chip connection, solder bumps
• CPC Class Codes: H01L 2225/06541 Conductive via connections through the device, e.g. vertical interconnects, through silicon via [TSV] manufacturing via connections per se H01L21/76898
• CPC Class Codes: H01L 2225/06548 Conductive via connections through the substrate, container, or encapsulation
• CPC Class Codes: H01L 2225/06551 Conductive connections on the side of the device
• CPC Class Codes: H01L 2225/06562 at least one device in the stack being rotated or offset
• CPC Class Codes: H01L 2225/06572 Auxiliary carrier between devices, the carrier having an electrical connection structure
• CPC Class Codes: H01L 2225/06589 Thermal management, e.g. cooling
• CPC Class Codes: H01L 23/42 : Fillings or auxiliary members in containers or encapsulations selected or arranged to facilitate heating or cooling
• CPC Class Codes: H01L 24/05 : of an individual bonding area
• CPC Class Codes: H01L 24/06 : of a plurality of bonding areas
• CPC Class Codes: H01L 24/13 : of an individual bump connector
• CPC Class Codes: H01L 24/16 : of an individual bump connector
• CPC Class Codes: H01L 24/29 : of an individual layer connector
• CPC Class Codes: H01L 24/32 : of an individual layer connector
• CPC Class Codes: H01L 24/73 : Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
• CPC Class Codes: H01L 24/81 : using a bump connector
• CPC Class Codes: H01L 24/92 : Specific sequence of method steps
• CPC Class Codes: H01L 25/0657 : Stacked arrangements of devices
• CPC Class Codes: H01L 25/50 : Multistep manufacturing processes of assemblies consisting of devices, each device being of a type provided for in group H01L27/00 or H01L29/00 H01L21/50 takes precedence
• CPC Class Codes: H01L 2924/01006 : Carbon [C]
• CPC Class Codes: H01L 2924/01013 : Aluminum [Al]
• CPC Class Codes: H01L 2924/01033 : Arsenic [As]
• CPC Class Codes: H01L 2924/014 : Solder alloys
• CPC Class Codes: H01L 2924/10253 : Silicon [Si]
• CPC Class Codes: H01L 2924/1431 : Logic devices
• CPC Class Codes: H01L 2924/1434 : Memory
• CPC Class Codes: H01L 2924/15311 : being a ball array, e.g. BGA
• CPC Class Codes: H01L 2924/19041 : being a capacitor
• CPC Class Codes: H01L 2924/19042 : being an inductor
• CPC Class Codes: H01L 2924/19102 : in a stacked assembly with the semiconductor or solid state device

Abstract

An assembly component and a technique for assembling a chip package using the assembly component are described. This chip package includes a set of semiconductor dies that are arranged in a stack in a vertical direction, which are offset from each other in a horizontal direction to define a stepped terraced at one side of the vertical stack. Moreover, the chip package may be assembled using the assembly component. In particular, the assembly component may include a housing having another stepped terrace. This other stepped terrace may include a sequence of steps in the vertical direction, which are offset from each other in the horizontal direction. Furthermore, the housing may be configured to mate with the set of semiconductor dies such that the set of semiconductor dies are arranged in the stack in the vertical direction. For example, the other stepped terrace may approximately be a mirror image of the stepped terrace.

Claims

1. An assembly component, comprising a housing that includes a first stepped terrace, wherein the first stepped terrace includes a sequence of steps in a vertical direction,

wherein each step after a first step in the sequence of steps is offset in a horizontal direction by a first offset value from an immediately preceding step in the sequence of steps,

wherein the housing is configured to mate with a set of semiconductor dies such that the set of semiconductor dies are arranged in a stack in the vertical direction, which is substantially perpendicular to a first semiconductor die in the vertical stack, and

wherein each semiconductor die, after the first semiconductor die, is offset in the horizontal direction by a second offset value from an immediately preceding semiconductor die in the vertical stack, thereby defining a second stepped terrace at one side of the vertical stack.

2. The assembly component of claim 1, wherein the first stepped terrace is approximately a mirror image of the second stepped terrace.

3. The assembly component of claim 1, wherein a given semiconductor die in the set of semiconductor dies has a nominal thickness;

and

wherein a vertical displacement of a given step in the sequence of steps is larger than the nominal thickness.

4. The assembly component of claim 1, wherein the first offset value is larger than the second offset value.

5. The assembly component of claim 1, wherein the assembly component facilitates assembly of a chip package in which a ramp component is rigidly mechanically coupled to the semiconductor dies,

wherein the ramp component is positioned on the one side of the vertical stack, and

wherein the ramp component is approximately parallel to a direction along the second stepped terrace, which is between the horizontal direction and the vertical direction.

6. The assembly component of claim 5, wherein the first offset value and the second offset value are determined based on the direction and a nominal thickness of solder used to rigidly mechanically couple the ramp component to the set of semiconductor dies.

7. The assembly component of claim 1, wherein the assembly component facilitates assembly of the set of semiconductor dies with an accumulated position error over the set of semiconductor dies in the vertical direction that is less than a sum of vertical errors associated with the set of semiconductor dies and a set of adhesive layers between the semiconductor dies.

8. The assembly component of claim 7, wherein the accumulated position error is associated with thickness variation of the semiconductor dies.

9. The assembly component of claim 7, wherein the accumulated position error is associated with thickness variation of the set of adhesive layers.

10. The assembly component of claim 7, wherein the accumulated position error is associated with thickness variation of a heat-spreading material in the set of adhesive layers.

11. The assembly component of claim 1, wherein the assembly component facilitates assembly of the set of semiconductor dies with a maximum position error associated with edge variation of the semiconductor dies that is less than a predefined value.

12. A method for assembling a chip package, comprising:

positioning an edge of a first semiconductor die in a vertical stack of semiconductor dies proximate to a first step in a sequence of steps in a first stepped terrace in a vertical direction of a housing, wherein the vertical direction is substantially perpendicular to the first semiconductor die;

applying an adhesive layer to a top surface of the first semiconductor die;

positioning an edge of a second semiconductor die in the vertical stack of semiconductor dies proximate to a second step in the sequence of steps in the vertical direction of the housing, wherein a bottom surface of the second semiconductor die is mechanically coupled to the adhesive layer, wherein the second step is offset in a horizontal direction by a first offset value from the first step, and wherein the second semiconductor die is offset in the horizontal direction by a second offset value, thereby defining a second stepped terrace at one side of the vertical stack; and

rigidly mechanically coupling a ramp component to the first semiconductor die and the second semiconductor die, wherein the ramp component is positioned on the one side of the vertical stack, and

wherein the ramp component is approximately parallel to a direction along the second stepped terrace, which is between the horizontal direction and the vertical direction.

13. The method of claim 12, wherein positioning a given semiconductor die, which can be one of the first semiconductor die and the second semiconductor die, involves a pick-and-place tool.

14. The method of claim 12, wherein positioning a given semiconductor die, which can be one of the first semiconductor die and the second semiconductor die, is based on optical alignment markers on the given semiconductor die.

15. The method of claim 12, wherein the adhesive layer includes a heat-spreading material that preferentially conducts heat in a plane of a given semiconductor die.

16. The method of claim 12, wherein rigidly mechanically coupling the ramp component to the first semiconductor die and the second semiconductor die involves melting solder on one of:

the ramp component, the first semiconductor die and the second semiconductor die, and both the ramp component and the first semiconductor die and the second semiconductor die.

17. The method of claim 12, wherein rigidly mechanically coupling the ramp component to the first semiconductor die and the second semiconductor die involves applying a compressive force in the vertical direction.

18. The method of claim 12, wherein the first stepped terrace is approximately a mirror image of the second stepped terrace.

19. The method of claim 12, wherein a given semiconductor die, which can be one of the first semiconductor die and the second semiconductor die, has a nominal thickness;

and

wherein a vertical displacement of a given step in the sequence of steps is larger than the nominal thickness.

20. A method for assembling a chip package, comprising:

positioning a first semiconductor die in a vertical stack of semiconductor dies, wherein the vertical stack is along a vertical direction that is substantially perpendicular to the first semiconductor die;

applying an adhesive layer to a top surface of the first semiconductor die;

positioning an edge of a second semiconductor die in the vertical stack of semiconductor dies relative to the first semiconductor die, wherein a bottom surface of the second semiconductor die is mechanically coupled to the adhesive layer, and wherein the second semiconductor die is offset in a horizontal direction by an offset value, thereby defining a stepped terrace at one side of the vertical stack; and

rigidly mechanically coupling a ramp component to the first semiconductor die and the second semiconductor die, wherein the ramp component is positioned on the one side of the vertical stack, and

wherein the ramp component is approximately parallel to a direction along the stepped terrace, which is between the horizontal direction and the vertical direction.