OUTPUT SWITCHING CIRCUIT

• US 20120049811A1
• Filed: 05/27/2011
• Published: 03/01/2012
• Est. Priority Date: 08/31/2010
• Status: Active Grant

• Current Assignee: Monterey Research, LLC (Vector Capital Corporation)
• Original Assignee: Fujitsu Semiconductor Limited (Fujitsu Limited)
• Inventors: WAKII, Takeshi, Yoshioka, Akihito
• Granted Patent: US 8,957,648 B2
• Time in Patent Office: Days
• US Class Current: 323/271
• CPC Class Codes: H02M 3/158 including plural semiconductor devices as final control devices for a single load
• CPC Class Codes: H02M 3/1588 comprising at least one synchronous rectifier element H02M3/1582, H02M3/1584 take precedence
• CPC Class Codes: H03K 17/6872 using complementary field-effect transistors
• CPC Class Codes: Y02B 70/10 Technologies improving the efficiency by using switched-mode power supplies [SMPS], i.e. efficient power electronics conversion e.g. power factor correction or reduction of losses in power supplies or efficient standby modes

Abstract

An output switching circuit includes a switching circuit having a first transistor connected to a high-voltage power supply, a second transistor connected to a low-voltage power supply, and an output terminal at a connection node between the first and second transistors; a comparison unit that compares an input signal with a feedback signal obtained by feedback of an output signal of the output terminal via a low-pass filter to generate a comparison signal; and a drive pulse generating unit that generates first drive pulses for driving the first transistor and second drive pulses for driving the second transistor in accordance with the comparison signal.

Claims

1. An output switching circuit comprising:

a switching circuit having a first transistor connected to a high-voltage power supply, a second transistor connected to a low-voltage power supply, and an output terminal at a connection node between the first and second transistors;

a comparison unit that compares an input signal with a feedback signal obtained by feedback of an output signal of the output terminal via a low-pass filter to generate a comparison signal; and

a drive pulse generating unit that generates first drive pulses for driving the first transistor and second drive pulses for driving the second transistor in accordance with the comparison signal.

2. The output switching circuit according to claim 1, wherein the comparison unit includes:

a comparator that compares the feedback signal with the input signal;

a sampling circuit that samples an output of the comparator with a reference clock to generate a sampling signal having a first or second level; and

a comparison signal generating circuit that generates, for each first period, the comparison signal having the first or second level and having a pulse width of the first period, in accordance with a pulse width of the first level or second level of the sampling signal.

3. The output switching circuit according to claim 2, wherein

while the comparison signal is at a first level indicating that a voltage of the input signal is higher than a voltage of the feedback signal, the drive pulse generating unit generates the first drive pulse obtained by pulse density modulation of this comparison signal.

4. The output switching circuit according to claim 2, wherein

while the comparison signal is at a second level indicating that a voltage of the input signal is lower than a voltage of the feedback signal, the drive pulse generating unit generates the second drive pulse obtained by pulse density modulation of this comparison signal.

5. The output switching circuit according to claim 2, wherein

while the comparison signal is at a first level indicating that a voltage of the input signal is higher than a voltage of the feedback signal, the drive pulse generating unit generates the first drive pulse having a pulse train with a frequency higher than that of the first period.

6. The output switching circuit according to claim 2, wherein

while the comparison signal is at a second level indicating that a voltage of the input signal is lower than a voltage of the feedback signal, the drive pulse generating unit generates the second drive pulse having a pulse train with a frequency higher than that of the first period.

7. The output switching circuit according to claim 5, wherein

while the comparison signal is at the first level, the drive pulse generating unit gradually increases a time in which the first transistor is conducive in the first drive pulse for each second period that is shorter than the first period.

8. The output switching circuit according to claim 7, wherein

when the comparison signal assumes the first level, the drive pulse generating unit controls the number of conduction pulses of the first transistor in the first drive pulse in an initial second period to a first number, and then gradually increases a conduction pulse width of the first transistor by replacing non-conduction pulses of the first transistor in the first drive pulse with the conduction pulses for each second period.

9. The output switching circuit according to claim 8, wherein

the drive pulse generating unit gradually increases a conduction pulse width of the first transistor in a second half of the second period.

10. The output switching circuit according to claim 7, wherein

when the comparison signal repeats a plurality of times a change in which the comparison signal is switched from the second level to the first level, maintained at the first level within a plurality of the second periods, and then switched from the first level to the second level, the drive pulse generating unit further increases the time in which the first transistor is conductive in the first drive pulse in an initial second period.

11. The output switching circuit according to claim 6, wherein

while the comparison signal is at the second level, the drive pulse generating unit gradually increases a time in which the second transistor is conducive in the second drive pulse for each second period that is shorter than the first period.

12. The output switching circuit according to claim 11, wherein

when the comparison signal assumes the second level, the drive pulse generating unit controls the number of conduction pulses of the second transistor in the second drive pulse in an initial second period to a second number, and then gradually increases a conduction pulse width of the second transistor by replacing non-conduction pulses of the second transistor in the second drive pulse with the conduction pulses for each second period.

13. The output switching circuit according to claim 12, wherein

the drive pulse generating unit gradually increases a conduction pulse width of the second transistor in a second half of the second period.

14. The output switching circuit according to claim 11, wherein

when the comparison signal assumes the second level, the drive pulse generating unit gradually increases the number of conduction pulses of the second transistor in the second drive pulse for each second period.

15. The output switching circuit according to claim 14, wherein

the drive pulse generating unit gradually increases the number of conduction pulses of the second transistor in a second half of the second period.

16. The output switching circuit according to claim 11, wherein

when the comparison signal repeats a plurality of times a change in which the comparison signal is switched from the first level to the second level, maintained at the second level within a plurality of the second periods, and then switched from the second level to the first level, the drive pulse generating unit further increases the time in which the second transistor is conductive in the second drive pulse in an initial second period.