Switched-Mode Converter

• US 20120049812A1
• Filed: 08/24/2011
• Published: 03/01/2012
• Est. Priority Date: 08/26/2010
• Status: Abandoned Application

• Current Assignee: STMicroelectronics SA (STMicroelectronics NV)
• Original Assignee: STMicroelectronics SA (STMicroelectronics NV)
• Inventors: Pinon, Vincent, Hasbani, Frédéric
• Application Number:
  US13/217,065
• Publication Number:
  US 20120049812A1
• Time in Patent Office: Days
• US Class Current: 323/271
• CPC Class Codes: H02M 1/08 Circuits specially adapted for the generation of control voltages for semiconductor devices incorporated in static converters
• CPC Class Codes: H02M 1/38 Means for preventing simultaneous conduction of switches

Abstract

A switched-mode converter includes first and second chopper transistors, and control means for maintaining the first and second chopper transistors respectively on and off during first operating phases. The first and second chopper transistors are maintained respectively off and on during second operating phases. An intermediary voltage is applied to the gate of the second transistor during intermediary phases taking place between the first and second phases. This intermediary voltage is close to the threshold voltage of the second transistor.

Claims

1. A switched-mode converter comprising:

a first chopper transistor;

a second chopper transistor; and

control means for;

maintaining the first and second chopper transistors respectively on and off during first operating phases;

maintaining the first and second transistors respectively off and on during second operating phases; and

applying an intermediary voltage to a gate of the second transistor during intermediary phases taking place between the first and second operating phases, the intermediary voltage being close to a threshold voltage of the second chopper transistor.

2. The converter of claim 1, wherein the first chopper transistor is a P-channel MOS transistor and the second chopper transistor is an N-channel MOS transistor, the first and second chopper transistors coupled in series between a high terminal and a low terminal of the converter.

3. The converter of claim 2, wherein the intermediary voltage is smaller than the threshold voltage of the second transistor by 50 mV to 150 mV.

4. The converter of claim 1, wherein the intermediary phases have a duration ranging between 1% and 10% of a full switching cycle period of the converter.

5. The converter of claim 1, wherein the control means comprises:

a first switch for connecting a gate of the first transistor to a terminal at a first voltage during the first operating phases, and to a terminal at a second voltage during the second operating phases and the intermediary phases;

a second switch for connecting the gate of the second transistor to a terminal at a third voltage during the first operating phases, to a terminal at a fourth voltage during the second operating phases, and to an intermediary node during the intermediary phases; and

means for applying the intermediary voltage to the intermediary node during the intermediary phases.

6. The converter of claim 5, wherein the means for applying the intermediary voltage comprise a diode-assembled transistor, biased by a current source.

7. The converter of claim 1, wherein the converter is connected as a voltage step-down transformer.

8. The converter of claim 1, wherein the converter is connected as a voltage step-up transformer.

9. The converter of claim 1, wherein the converter is connected as a class-D amplifier.

10. A switched-mode converter comprising:

a first chopper transistor;

a second chopper transistor; and

control circuitry configured to maintain the first chopper transistor on and the second chopper transistor off during first operating phases, to maintain the first chopper transistor off and the second chopper transistor on during second operating phases, and to apply an intermediary voltage to a control terminal of the second chopper transistor during intermediary phases that take place between the first and second operating phases, the intermediary voltage being close to a threshold voltage of the second chopper transistor.

11. The converter of claim 10, wherein the first chopper transistor is a P-channel MOS transistor and the second chopper transistor is an N-channel MOS transistor, the first and second chopper transistors coupled in series between a high terminal and a low terminal of the converter.

12. The converter of claim 11, wherein the intermediary voltage is smaller than the threshold voltage of the second chopper transistor by 50 mV to 150 mV.

13. The converter of claim 10, wherein the intermediary phases have a duration ranging between 1% and 10% of a full switching cycle period of the converter.

14. The converter of claim 10, wherein the control circuitry comprises:

a first switch for connecting a control terminal of the first chopper transistor to a terminal at a first voltage during the first operating phases, and to a terminal at a second voltage during the second operating phases and the intermediary phases; and

a second switch for connecting the control terminal of the second chopper transistor to a terminal at a third voltage during the first phases, to a terminal at a fourth voltage during the second operating phases, and to an intermediary node during the intermediary phases.

15. The converter of claim 14, wherein the control circuitry further comprises a circuit configured to apply the intermediary voltage to the intermediary node during the intermediary phases.

16. The converter of claim 14, wherein the control circuitry further comprises means for applying the intermediary voltage to the intermediary node during the intermediary phases.

17. The converter of claim 14, wherein the control circuitry further comprises a diode-connected transistor coupled to a control terminal of the second switch.

18. The converter of claim 17, wherein the diode-connected transistor is biased by a current source.

19. The converter of claim 10, wherein the converter is connected as a voltage step-down transformer.

20. The converter of claim 10, wherein the converter is connected as a voltage step-up transformer.

21. The converter of claim 10, wherein the converter is connected as a class-D amplifier.

22. A circuit comprising:

a first transistor having a current path between a first source/drain region and a second source/drain region and a gate, the first source/drain region coupled to a first input terminal;

a second transistor having a current path between a first source/drain region and a second source/drain region and a gate, the first source/drain region coupled to a second input terminal and the current path of the second transistor coupled in series with the current path of the first transistor;

a diode-connected transistor having a current path between a first source/drain region and a second source/drain region and a gate, the second source/drain region of the diode-connected transistor being coupled to the gate of the diode-connected transistor;

a current source coupled in series with the current path of the diode-connected transistor between the first input terminal and the second input terminal;

a first switch coupled to the gate of the first transistor so as to connect the gate to either a gate high voltage terminal or to a gate low voltage terminal; and

a second switch coupled to the gate of the second transistor so as to connect the gate to either the gate high voltage terminal or to a gate low voltage terminal or the gate of the diode-connected transistor.

23. The circuit of claim 22, further comprising:

an inductor with a first terminal coupled to the second source/drain region of the first and second transistors; and

a capacitor with a first terminal coupled to a second terminal of the inductor.

24. The circuit of claim 23, wherein the capacitor further includes a second terminal coupled to the second input terminal, the second input terminal comprising a ground terminal.

25. The circuit of claim 24, wherein the gate low voltage terminal also comprises a ground terminal and wherein the gate high voltage terminal is connected to the first input terminal.

26. The circuit of claim 22, further comprising a third switch coupled with a current path coupled in series with the current source and the diode-connected transistor.

27. The circuit of claim 22, wherein the first transistor is a P-channel MOS transistor and the second transistor is an N-channel MOS transistor.

28. A circuit comprising:

a first transistor having a current path between a first source/drain region and a second source/drain region and a gate, the first source/drain region coupled to a first input terminal;

a second transistor having a current path between a first source/drain region and a second source/drain region and a gate, the first source/drain region coupled to a second input terminal and the current path of the second transistor coupled in series with the current path of the first transistor;

a third transistor having a current path between a first source/drain region and a second source/drain region and a gate, the second source/drain region of the third transistor being coupled to the gate of the third transistor;

a first switch coupled to the gate of the first transistor so as to connect the gate to either a gate high voltage terminal or to a gate low voltage terminal;

a second switch coupled to the gate of the second transistor so as to connect the gate to either the gate high voltage terminal or to the gate low voltage terminal or the gate of the third transistor;

a fourth transistor having a current path between a first source/drain region and a second source/drain region and a gate, the current path of the fourth transistor coupled in series with the current path of the third transistor;

a third switch with a current path coupled in series with the current path of the third transistor and the current path of the fourth transistor;

a fifth transistor having a current path between a first source/drain region and a second source/drain region and a gate, the second source/drain region of the fifth transistor being coupled to the gate of the fifth transistor and the gate of the fifth transistor being coupled to the gate of the fourth transistor;

a sixth transistor having a current path between a first source/drain region and a second source/drain region and a gate, the second source/drain region of the sixth transistor being coupled to the gate of the sixth transistor; and

a current source coupled in series with the current paths of the fifth transistor and the sixth transistor.

29. The circuit of claim 28, further comprising:

an inductor with a first terminal coupled to the second source/drain region of the first and second transistors; and

a capacitor with a first terminal coupled to a second terminal of the inductor.

30. The circuit of claim 29, wherein the capacitor further includes a second terminal coupled to the second input terminal, the second input terminal comprising a ground terminal.

31. The circuit of claim 30, wherein the gate low voltage terminal also comprises a ground terminal and wherein the gate high voltage terminal is connected to the first input terminal.

32. The circuit of claim 28, wherein the first transistor is a P-channel MOS transistor and the second transistor is an N-channel MOS transistor.

33. The circuit of claim 28, further comprising:

a fourth switch coupled between the second source/drain region of the third transistor and the gate of the third transistor; and

a fifth switch coupled between the gate of the third transistor and the gate high voltage terminal.

34. The circuit of claim 33, further comprising:

an inductor with a first terminal coupled to the second source/drain region of the first and second transistors; and

a capacitor with a first terminal coupled to a second terminal of the inductor and a second terminal coupled to the second input terminal;

wherein the second input terminal comprises a ground terminal;

wherein the gate low voltage terminal also comprises a ground terminal; and

wherein the gate high voltage terminal is connected to the first input terminal.

35. A method of operating a converter that comprises a first chopper transistor coupled in series with a second chopper transistor between input terminals, the method comprising:

maintaining the first chopper transistor on and the second chopper transistor off during first operating phases;

maintaining the first chopper transistor off and the second chopper transistor on during second operating phases; and

applying an intermediary voltage to a gate of the second chopper transistor during intermediary phases that take place between the first and second operating phases, the intermediary voltage being close to a threshold voltage of the second chopper transistor.

36. The method of claim 35, wherein the first chopper transistor is a P-channel MOS transistor and the second chopper transistor is an N-channel MOS transistor.

37. The method of claim 36, wherein the intermediary voltage is smaller than the threshold voltage of the second transistor by 50 mV to 150 mV.

38. The method of claim 35, wherein the intermediary phases have a duration ranging between 1% and 10% of a full switching cycle period of the converter.

39. The method of claim 35, wherein the intermediary phases have a duration ranging between 1 ns and 5 ns.

40. The method of claim 39, wherein the intermediary phases have a duration ranging between 1% and 10% of a full switching cycle period of the converter.