HYSTERESIS COMPARATOR

• US 20120049892A1
• Filed: 03/15/2011
• Published: 03/01/2012
• Est. Priority Date: 08/26/2010
• Status: Active Grant

• Current Assignee: Kabushiki Kaisha Toshiba (Toshiba Corporation)
• Original Assignee: Kabushiki Kaisha Toshiba (Toshiba Corporation)
• Inventors: Ueno, Masaji
• Granted Patent: US 8,368,429 B2
• Time in Patent Office: Days
• US Class Current: 327/72
• CPC Class Codes: H03K 5/1532 Peak detectors measuring characteristics of individual pulses G01R29/02

Abstract

According to one embodiment, a hysteresis comparator is provided with to first to third current sources, a comparison amplifying unit, a reference voltage generating unit, a current mirror circuit, first to fifth N-channel MOS transistors, and first to fifth terminals.

Claims

1. A hysteresis comparator, comprising:

a reference voltage generating unit to be applied with a first voltage on one end side, the reference voltage generating unit to divide the first voltage by use of a plurality of resistors, the reference voltage generating unit to generate a reference voltage;

a comparison amplifying unit provided between a high potential power supply and a low potential power supply, the comparison amplifying unit having first and second transistors composing of a differential pair, the first transistor having a gate receiving an input voltage, the second transistor having a gate receiving the reference voltage;

a third transistor provided between the other end of the reference voltage generating unit and the low potential power supply;

a fourth transistor provided between the high potential power supply and the low potential power supply, the fourth transistor having a gate receiving an output signal of the comparison amplifying unit;

a first current source having one end connected to the high potential power supply, the first current to allow a first current to flow to the other end side;

a fifth transistor having a first terminal connected to the other end of the first current source, the fifth transistor being diode-connected;

a sixth transistor provided between a second terminal of the fifth transistor and the other end of the reference voltage generating unit, the sixth transistor having a gate connected to a gate of the third transistor and a first terminal of the forth transistor, the sixth transistor to connect between the second terminal of the fifth transistor and the other end of the reference voltage generating unit based on a potential of the first terminal of the fourth transistor;

a second current source having one end connected to the high potential power supply, the second current source to allow a second current to flow to the other end side, the second current being n times (n is 2 or larger) as large as the first current;

a seventh transistor having a first terminal connected to the other end of the second current source, the seventh transistor having a gate connected to a gate of the fifth transistor, the seventh transistor to constitute a current mirror circuit with the fifth transistor, the seventh transistor to output an output voltage; and

eighth and ninth transistors provided between a second terminal of the seventh transistor and the low potential power supply, the eighth and ninth transistors being cascade-connected, the eighth and ninth transistors to turn on during an operation of the comparison amplifying unit.

2. The hysteresis comparator according to claim 1, wherein the first and second transistors are P-channel MOS transistors, an output signal of the comparison amplifying unit is a noninverted output signal, and the third to ninth transistors are N-channel MOS transistors.

3. The hysteresis comparator according to claim 2, wherein

the comparison amplifying unit further includes a third current source, a first N-channel MOS transistor and a second N-channel MOS transistor,

one end of the third current source is connected to the high potential power supply, the other end of the third current source is connected to first terminals of the first and second transistors, and the third current source allows a third current to flow to the first terminal sides of the first and second transistors,

a first terminal of the first N-channel MOS transistor is connected to a second terminal of the first transistor, and a second terminal of the first N-channel MOS transistor is connected to the low potential power supply, and

a first terminal of the second N-channel MOS transistor is connected to a second terminal of the second transistor, a gate of the second N-channel MOS transistor is connected to the first terminal of the second N-channel MOS transistor and a gate of the first N-channel MOS transistor, and a second terminal of the second N-channel MOS transistor is connected to the low potential power supply.

4. The hysteresis comparator according to claim 3, further comprising

a forth current source having one terminal connected to the high potential power supply, the forth current source having the other end connected to a first terminal of the fourth transistor, the forth current source to allow a forth current to flow to the first terminal side of the fourth transistor.

5. The hysteresis comparator according to claim 1, wherein the first and second transistors are N-channel MOS transistors, an output signal of the comparison amplifying unit is a inverted output signal, and the third to ninth transistors are N-channel MOS transistors.

6. The hysteresis comparator according to claim 1, wherein

the comparison amplifying unit is composed of cascade-connected first and second resistors,

the gate of the second transistor is connected between the first and second resistors, and

when a value of the first resistor is referred to as R1, a value of the second resistor as R2, the first voltage as V1 and a hysteresis width of the hysteresis comparator as Vhys, the hysteresis width is expressed as

Vhys=V1×

{R1+R2)}.

7. The hysteresis comparator according to claim 1, wherein, after a level of the output signal of the comparison amplifying unit changed and then the reference voltage changed due to a hysteresis operation, the level of the output signal changes.

8. A hysteresis comparator, comprising:

a reference voltage generating unit to be applied with a first voltage on one end side, the reference voltage generating unit to divide the first voltage by use of a plurality of resistors, the reference voltage generating unit to generate a reference voltage;

a comparison amplifying unit provided between a high potential power supply and a low potential power supply, the comparison amplifying unit having first and second transistors composing of a differential pair, the first transistor having a gate receiving an input voltage, the second transistor having a gate receiving the reference voltage;

a third transistor provided between the high potential power supply and the other end of the reference voltage generating unit;

a fourth transistor provided between the high potential power supply and the low potential power supply, the fourth transistor having a gate receiving an output signal of the comparison amplifying unit;

a fifth transistor having a second terminal connected to a gate of the fifth transistor, the fifth transistor being diode-connected;

a first current source having one end connected to the second terminal of the fifth transistor, the first current source having the other end connected to the low potential power supply, the first current source to allow a first current to flow to the other end side;

a sixth transistor provided between a first terminal of the fifth transistor and the other end of the reference voltage generating unit, the sixth transistor having a gate connected to a gate of the third transistor and a second terminal of the fourth transistor, the sixth transistor to connect between the first terminal of the fifth transistor and the other end of the reference voltage generating unit based on a potential of a second terminal of the fourth transistor;

a seventh transistor having a gate connected to the gate of the fifth transistor, the seventh transistors to constitute a current mirror circuit with the fifth transistor, the seventh transistor to output an output voltage;

eighth and ninth transistors provided between the high potential power supply and a first terminal of the seventh transistor, the eighth and ninth transistors being cascade-connected, the eighth and ninth transistors to turn on during an operation of the comparison amplifying unit; and

a second current source having one end connected to a second terminal of the seventh transistor, the second current source having the other end connected to low high potential power supply, the second current source to allow a second current to flow to the other end side, the second current being n times (n is 2 or larger) as large as the first current.

9. The hysteresis comparator according to claim 8, wherein the first and second transistors are N-channel MOS transistors, an output signal of the comparison amplifying unit is a noninverted output signal, and the third to ninth transistors are P-channel MOS transistors.

10. The hysteresis comparator according to claim 9, wherein

the comparison amplifying unit further includes a third current source, a first P-channel MOS transistor and a second P-channel MOS transistor,

one end of the third current source is connected to second terminals of the first and second transistors, the other end of the third current source is connected to the low potential power supply, and the third current source allows a third current to flow to the low potential power supply,

a first terminal of the first P-channel MOS transistor is connected to the high potential power supply, and a second terminal of the first P-channel MOS transistor is connected to a first terminal of the first transistor, and

a first terminal of the second P-channel MOS transistor is connected to the high potential power supply, a gate of the second P-channel MOS transistor is connected to a second terminal of the second P-channel MOS transistor and a gate of the first P-channel MOS transistor, and the second terminal of the first P-channel MOS transistor is connected to the first terminal of the second transistor.

11. The hysteresis comparator according to claim 10, further comprising

a fourth current source having one terminal connected to a second terminal of the fourth transistor, the fourth current source having the other end connected to the low potential power supply, the fourth current source to allow a fourth current to flow to the low potential power supply side.

12. The hysteresis comparator according to claim 8, wherein

the comparison amplifying unit is composed of cascade-connected first and second resistors,

the gate of the second transistor is connected between the first and second resistors, and

when a value of the first resistor is referred to as R1, a value of the second resistor as R2, the first voltage as V1 and a hysteresis width of the hysteresis comparator as Vhys, the hysteresis width is expressed as

Vhys=V1×

{R1/(R1+R2)}.

13. The hysteresis comparator according to claim 8, wherein, after a level of the output signal of the comparison amplifying unit changed and then the reference voltage changed due to a hysteresis operation, the level of the output signal changes.