LOW-LEAKAGE DIODES AND METHODS OF FORMING THE SAME

• US 20120049934A1
• Filed: 08/30/2010
• Published: 03/01/2012
• Est. Priority Date: 08/30/2010
• Status: Active Grant

• Current Assignee: Analog Devices, Inc.
• Original Assignee: Analog Devices, Inc.
• Inventors: Shih, David Hwa Chieh
• Granted Patent: US 8,441,305 B2
• Time in Patent Office: Days
• US Class Current: 327/534
• CPC Class Codes: H01L 27/0259 using bipolar transistors as protective elements
• CPC Class Codes: H01L 29/861 Diodes
• CPC Class Codes: H01L 29/93 Variable capacitance diodes, e.g. varactors

Abstract

Low leakage diodes and methods of forming the same are disclosed. In one embodiment an apparatus includes a designed or parasitic bipolar transistor having an emitter, a base and a collector. The bipolar transistor is configured to operate as a diode, the diode having reverse-biased and forward-biased modes of operation. The emitter and base operate as first and second terminals of the diode, respectively. The collector is configured to receive a collector bias voltage, which is controlled relative to a voltage of the emitter to reduce a diffusion leakage current of the diode when the diode is in the reverse-biased mode of operation.

Claims

1. An apparatus comprising:

a bipolar transistor configured to operate as a diode, wherein the diode can be biased in a forward-biased mode of operation, a reverse-biased mode of operation, and an equilibrium mode of operation, the bipolar transistor comprising;

an emitter for operating as a first terminal of the diode;

a base for operating as a second terminal of the diode; and

a collector for receiving a collector bias voltage, wherein the collector bias voltage is configured relative to a voltage of the emitter to minimize a diffusion leakage current of the diode when the diode is in the reverse-biased mode of operation.

2. The apparatus of claim 1, wherein the bipolar transistor is an NPN bipolar transistor, and wherein the first terminal of the diode is a cathode, and wherein the second terminal of the diode is an anode.

3. The apparatus of claim 1, wherein the bipolar transistor is a PNP bipolar transistor, and wherein the first terminal of the diode is an anode, and wherein the second terminal of the diode is a cathode.

4. The apparatus of claim 1, wherein the collector bias voltage is generated by a bias circuit.

5. The apparatus of claim 4, wherein the bias circuit comprises an operational amplifier having a positive input, a negative input, and an output, wherein the output is electrically connected to the collector and to the negative input, and wherein the positive input is electrically connected to the emitter.

6. The apparatus of claim 5, wherein an offset voltage of the operational amplifier between the positive input and the negative input has a magnitude less than about 10 mV.

7. The apparatus of claim 4, wherein the bias circuit comprises a gain circuit having an input and an output, wherein the output of the gain circuit is electrically connected to the collector, and wherein the input of the gain circuit is electrically connected to the emitter.

8. The apparatus of claim 4, wherein the bias circuit is configured to control the collector bias voltage so that a difference between the collector bias voltage and a voltage of the emitter has a magnitude less than about one-third kT/q when the diode is reverse-biased by a voltage ranging between about zero to about four times kT/q, wherein k is Boltzmann'"'"'s constant, T is temperature, and q is the magnitude of the charge of an electron.

9. The apparatus of claim 4, wherein the bias circuit is configured to control the collector bias voltage so that a difference between the collector bias voltage and a voltage of the emitter has a magnitude less than about 10 mV when the diode is reverse-biased by a voltage ranging between about 0 mV to about 100 mV.

10. The apparatus of claim 9, wherein the bias circuit is configured to bias the collector bias voltage such that a reverse bias voltage between the base and the collector is greater than about 90 mV when the diode is reverse-biased by a voltage greater than about 100 mV.

11. The apparatus of claim 1, wherein the apparatus comprises an integrated circuit.

12. The apparatus of claim 11, further comprising a bonding pad disposed on a surface of the integrated circuit, wherein the bonding pad is electrically connected to an internal circuit of the integrated circuit and to at least one of the emitter and base of the bipolar transistor, and wherein the bipolar transistor is configured to protect the internal circuit from electrostatic discharge events received on the pad.

13. The apparatus of claim 12, wherein the internal circuit is a complimentary metal-oxide-semiconductor (CMOS) amplifier.

14. The apparatus of claim 13, wherein the apparatus comprises a field effect transistor switch, the switch having a source, a drain, a gate, a semiconductor body, and an isolation structure disposed in a substrate, and wherein the source acts as the emitter of the bipolar transistor and the semiconductor body acts as the base of the bipolar transistor.

15. The apparatus of claim 14, wherein the source and drain are disposed in the semiconductor body, and wherein the gate is disposed between the source and drain adjacent a surface of the semiconductor body, and wherein the isolation structure surrounds the semiconductor body so as to electrically isolate the semiconductor body from the substrate.

16. The apparatus of claim 14, wherein the isolation structure acts as the collector of the bipolar transistor.

17. The apparatus of claim 13, wherein the switch is an n-type switch, and wherein the isolation structure comprises an n-well and an n-type buried layer.

18. A method for providing a diode, wherein the diode can be biased in a forward-biased mode of operation, a reverse-biased mode of operation, and an equilibrium mode of operation, the method comprising:

providing a bipolar transistor having an emitter, a base, and a collector;

configuring the emitter to operate as a first terminal of the diode;

configuring the base to operate as a second terminal of the diode; and

biasing a voltage of the collector relative to a voltage of the emitter to minimize a diffusion leakage current of the diode when the diode is in the reverse-biased mode of operation.

19. The method of claim 18, wherein the bipolar transistor is an NPN bipolar transistor, and wherein the first terminal of the diode is a cathode, and wherein the second terminal of the diode is an anode.

20. The method of claim 18, wherein biasing the collector comprises using a bias circuit.

21. The method of claim 20, wherein biasing the collector comprises biasing the voltage of the collector so that a difference between the voltage of the collector and the voltage of the emitter has a magnitude less than about 10 mV when the diode is reverse-biased by a voltage ranging between about 0 mV to about 100 mV.

22. The method of claim 18, further comprising protecting an integrated circuit having a bonding pad from an electrostatic discharge event by electrically connecting at least one of the emitter and base of the bipolar transistor to the bonding pad.