EQUALIZATION CIRCUIT

• US 20120049946A1
• Filed: 08/31/2010
• Published: 03/01/2012
• Est. Priority Date: 08/31/2010
• Status: Active Grant

• Current Assignee: Mosys Incorporated (Peraso, Inc.)
• Original Assignee: Mosys Incorporated (Peraso, Inc.)
• Inventors: Boecker, Charles W.
• Granted Patent: US 8,274,326 B2
• Time in Patent Office: Days
• US Class Current: 327/559
• CPC Class Codes: H03F 1/301 in MOSFET amplifiers H03F1/303, H03F1/305, H03F1/308 take precedence
• CPC Class Codes: H03F 2203/45082 the common mode signal being taken or deducted from the one or more outputs of the differential amplifier
• CPC Class Codes: H03F 2203/45544 the IC comprising one or more capacitors, e.g. coupling capacitors
• CPC Class Codes: H03F 2203/45594 the IC comprising one or more resistors, which are not biasing resistor
• CPC Class Codes: H03F 3/45179 using MOSFET transistors as the active amplifying circuit H03F3/45278 takes precedence
• CPC Class Codes: H03F 3/45632 in differential amplifiers with FET transistors as the active amplifying circuit H03F3/4578 takes precedence
• CPC Class Codes: H04L 2025/0349 as a feedback filter
• CPC Class Codes: H04L 25/03885 adaptive

Abstract

An equalization circuit is disclosed. The equalization circuit includes a first differential amplifier having first and second transistors, and a first differential high-pass filter coupled to respective gate terminals of the first and second transistors. A source terminal of the first transistor is coupled to a first input node, and a source terminal of the second transistor is coupled to the second input node. The equalization circuit further includes a second differential amplifier having third and fourth transistors, and a second differential high-pass filter coupled to respective gate terminals of each of the third and fourth transistors. A source terminal of the third transistor is coupled to the first input node, and a source terminal of the second transistor is coupled to the second input node. Using such a circuit, continuous time decision feedback equalization may be performed.

Claims

1. A circuit comprising:

a first differential amplifier having first and second transistors;

a first differential high-pass filter coupled to respective gate terminals of the first and second transistors, wherein a source terminal of the first transistor is coupled to a first input node, and wherein a source terminal of the second transistor is coupled to a second input node;

a second differential amplifier having third and fourth transistors; and

a second differential high-pass filter coupled to respective gate terminals of the third and fourth transistors, wherein a source terminal of the third transistor is coupled to the first input node, and wherein a source terminal of the fourth transistor is coupled to the second input node.

2. The circuit as recited in claim 1, wherein respective gate terminals of the first and second transistors are coupled to receive, via the first differential high-pass filter, signals having opposite polarities from the signals received at their respective source terminals;

and

wherein respective gate terminals of the third and fourth transistors are coupled to receive, via the second differential high-pass filter, signals having opposite polarities from the signals received at their respective source terminals.

3. The circuit as recited in claim 2, wherein the first differential high-pass filter includes:

a first capacitor coupled between a gate terminal of the first transistor and the second input node;

a second capacitor coupled between a gate terminal of the second transistor and the first input node;

a first resistor coupled between the gate terminal of the first transistor and a bias node; and

a second resistor coupled between the gate terminal of the second transistor and the bias node;

wherein the second differential high-pass filter includes;

a third capacitor coupled between a gate terminal of the third transistor and the second input node;

a fourth capacitor coupled between a gate terminal of the fourth transistor and the first input node;

a third resistor coupled between the gate terminal of the third transistor and a common mode feedback node; and

a fourth resistor coupled between the gate terminal of the fourth resistor and the common mode feedback node.

4. The circuit as recited in claim 3, wherein the circuit further includes an output circuit having a first intermediate node coupled to a drain terminal of the third transistor and a second intermediate node coupled to a drain terminal of the fourth transistor, wherein the output circuit includes:

a first plurality of inverters coupled in series between the first intermediate node and a first output node; and

a second plurality of inverters coupled in series between the second intermediate node and a second output node.

5. The circuit as recited in claim 4, wherein the output circuit further includes a first feedback resistor coupled between the first intermediate node and the second output node, and a second feedback resistor coupled between the second intermediate node and the first output node.

6. The circuit as recited in claim 4, wherein the circuit further includes a bias/feedback circuit coupled to receive first and second output signals from the first and second output nodes, respectively, and wherein the bias/feedback circuit is further coupled to provide a bias voltage on the bias node and a common mode feedback voltage on the common mode feedback node.

7. The circuit as recited in claim 1, wherein the circuit further includes:

a first current mirror having fifth and sixth transistors, wherein a drain terminal of the fifth transistor is coupled to a drain terminal of the second transistor and a drain terminal of the sixth transistor is coupled to a drain terminal of the third transistor, wherein the first current mirror further includes a first resistor coupled between gate terminals of the fifth and sixth transistors; and

a second current mirror having seventh and eighth transistors, wherein a drain terminal of the seventh transistor is coupled to a drain terminal of the first transistor and wherein a drain terminal of the eighth transistor is coupled between a drain terminal of the fourth transistor, and wherein the current second current mirror further includes a second resistor coupled between gate terminals of the seventh and eighth transistors.

8. The circuit as recited in claim 7, further comprising a first termination resistor coupled to the first input node, and a second termination resistor coupled between the first termination resistor and the second input node.

9. The circuit as recited in claim 8, further comprising a decoupling capacitor coupled between a junction of the first and second termination resistors and a ground node.

10. A method comprising:

receiving a first signal at both a source terminal a first transistor of a first differential amplifier and at a source terminal of a third transistor of a second differential amplifier;

receiving a second signal at both a source terminal of a second transistor of the first differential amplifier and at a source terminal of a fourth transistor of the second differential amplifier;

high-pass filtering, in first and second differential high-pass filters, the first signal to generate filtered versions of the first signal at respective gate terminals of the second and fourth transistors;

high-pass filtering, in the first and second differential high-pass filters, the second signal to generate filtered versions of the second signal at respective gate terminals of the first and third transistors;

amplifying, in each of the first and second differential amplifiers, a difference between filtered versions of the first and second signals; and

generating a differential output signal based on said amplifying.

11. The method as recited in claim 10, wherein generating the differential output signal comprises:

a first plurality of serially-coupled inverters receiving a seventh signal from a drain terminal of the third transistor;

a second plurality of serially-coupled inverters receiving an eighth signal from a drain terminal of the fourth transistor;

the first plurality of serially-coupled inverters generating a first output signal based on the seventh signal; and

the second plurality of serially-coupled inverters generating a second output signal based on the eight signal, the second output signal having a polarity opposite of the first output signal, wherein the differential output signal comprises the first and second output signals.

12. The method as recited in claim 11, further comprising:

a first current mirror mirroring current passing through a drain terminal of the second transistor, wherein the first current mirror includes a fifth transistor having a drain terminal coupled to the drain terminal of the second transistor, a sixth transistor coupled to the drain terminal of the third transistor; and

a second current mirror mirroring current passing through a drain terminal of the first transistor, wherein the second current mirror includes a seventh transistor having a drain terminal coupled to the drain terminal of the first transistor, and an eighth transistor having a drain terminal coupled to the drain terminal of the fourth transistor.

13. The method as recited claim 11, further comprising:

a bias/feedback circuit receiving the first and second output signals;

the bias/feedback circuit generating a common mode feedback voltage based on the first and second output signals; and

the bias/feedback circuit generating a bias voltage.

14. The method as recited in claim 13, further comprising the first differential high-pass filter receiving the bias voltage and the second differential high-pass filter receiving the common mode feedback voltage.

15. The method as recited in claim 11, further comprising:

providing the first output signal as feedback, through a first feedback resistor, to an input of the second plurality of serially-coupled inverters; and

providing the second output signal as feedback, through a second feedback resistor, to an input of the first plurality of serially-coupled inverters.

16. An apparatus comprising:

first means for high-pass filtering a differential input signal including a first signal and a second signal;

second means for amplifying a difference between the first signal and a high-pass filtered version of the second signal received from said first means and for amplifying a difference between the second signal and a high-pass filtered version of the first signal received from said first means;

third means for high-pass filtering the differential input signal; and

fourth means for amplifying a difference between the first signal and a high-pass filtered version of the second signal received from said third means and for amplifying a difference between the second signal and a high-pass filtered version of the first signal received from said third means.

17. The apparatus as recited in claim 16, wherein the apparatus further includes fifth means for generating a differential output signal based on said amplifying performed by said second means and said amplifying performed by said fourth means.

18. The apparatus as recited in claim 17, further comprising:

sixth means for mirroring a first current passing through said second means, wherein said sixth means is coupled between said second means and said fourth means; and

seventh means for mirroring a second current passing through said second means, wherein said seventh means is coupled between said second means and said fourth means.

19. The apparatus as recited in claim 18, further comprising eighth means for generating a common-mode feedback voltage and a bias current, wherein said eighth means is coupled to provide the common-mode feedback voltage to said third means, and further coupled to provide the bias voltage to said first means.

20. The apparatus as recited in claim 29, further comprising ninth means for terminating a first signal line conveying the first signal and for terminating a second signal line conveying the second signal.

21. A method comprising:

receiving first and second input signals;

amplifying, in first and second differential amplifiers, a difference between filtered versions of the first and second signals;

generating, based on said amplifying, a differential output having first and second full-rail digital output signals on first and second output paths, respectively;

providing the first full-rail digital output signal as continuous time feedback to an input of the second output path; and

providing the second output signal as continuous time feedback to an input of the first output path.

22. The method as recited in claim 21, further comprising providing the first full-rail digital output signal to the input of the second output path through a first feedback resistor, and providing the second full-rail digital output signal to the input of the first output path through a second feedback resistor.

23. The method as recited in claim 21, wherein said filtering comprises high-pass filtering the first and second signals.

24. The method as recited in claim 23, further comprising:

receiving a high-pass filtered version of the first signal at a gate terminal of a first transistor and the second signal at a source terminal of the first transistor;

receiving a high-pass filtered version of the second signal at a gate terminal of a second transistor and the first signal at a source terminal of the second transistor, wherein the first differential amplifier includes the first and second transistors;

receiving a high-pass filtered version of the first signal at a gate terminal of a third transistor and the second signal at a source terminal of the third transistor; and

receiving a high-pass filtered version of the second signal at a gate terminal of a fourth transistor and the first signal at a source terminal of the fourth transistor, wherein the second differential amplifier includes the third and fourth transistors.