INPUT/OUTPUT DEVICE

• US 20120050196A1
• Filed: 08/25/2011
• Published: 03/01/2012
• Est. Priority Date: 08/27/2010
• Status: Active Grant

• Current Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Original Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Inventors: Kurokawa, Yoshiyuki
• Granted Patent: US 8,928,053 B2
• Time in Patent Office: Days
• US Class Current: 345/173
• CPC Class Codes: G06F 3/041 Digitisers, e.g. for touch screens or touch pads, characterised by the transducing means
• CPC Class Codes: G09G 3/36 using liquid crystals
• CPC Class Codes: H04N 25/778 comprising amplifiers shared between a plurality of pixels, i.e. at least one part of the amplifier must be on the sensor array itself

Abstract

An input/output device includes a display circuit which changes its display state in accordance with a display data signal; a plurality of photodetector circuits which generate optical data in accordance with illuminance of light entering the photodetector circuits; wherein the photodetector circuits each include X (a natural number of 2 or more) photoelectric conversion elements; X charge accumulation control transistors in which one of a source and a drain is electrically connected to a second current terminal of one photoelectric conversion element of the X photoelectric conversion elements, and one charge accumulation control signal of X charge accumulation control signals from the photodetector circuit control section is input to the gate; and an amplifying transistor in which a gate is electrically connected to one of the source and the drain of each of the X charge accumulation control transistors.

Claims

1. A semiconductor device comprising:

a pixel portion configured to display an image, the pixel portion comprising;

a first photoelectric conversion element;

a second photoelectric conversion element;

a first transistor;

a second transistor; and

a third transistor,

wherein the first photoelectric conversion element is electrically connected to one of a source and a drain of the first transistor,

wherein the second photoelectric conversion element is electrically connected to one of a source and a drain of the second transistor,

wherein the other of the source and the drain of the first transistor is electrically connected to a gate of the third transistor, and

wherein the other of the source and the drain of the second transistor is electrically connected to the gate of the third transistor.

2. The semiconductor device according to claim 1,

wherein the first transistor is a first charge accumulation control transistor,

wherein the second transistor is a second charge accumulation control transistor, and

wherein the third transistor is an amplifying transistor.

3. The semiconductor device according to claim 1,

wherein the first transistor and the second transistor each comprise an oxide semiconductor layer comprising a channel formation region

4. The semiconductor device according to claim 3,

wherein a carrier concentration of the oxide semiconductor layer is lower than 1×

10¹⁴/cm³.

5. The semiconductor device according to claim 1,

wherein the third transistor comprises a semiconductor layer comprising a channel formation region comprising a semiconductor element belonging to Group 14 in the periodic table.

6. The semiconductor device according to claim 1,

wherein the pixel portion comprises a liquid crystal element.

7. A semiconductor device comprising:

a pixel portion configured to display an image, the pixel portion comprising;

a first photoelectric conversion element;

a second photoelectric conversion element;

a first transistor;

a second transistor;

a third transistor; and

a fourth transistor,

wherein the first photoelectric conversion element is electrically connected to one of a source and a drain of the first transistor,

wherein the second photoelectric conversion element is electrically connected to one of a source and a drain of the second transistor,

wherein the other of the source and the drain of the first transistor is electrically connected to a gate of the third transistor,

wherein the other of the source and the drain of the second transistor is electrically connected to the gate of the third transistor, and

wherein one of a source and a drain of the third transistor is electrically connected to one of a source and a drain of the fourth transistor.

8. The semiconductor device according to claim 7,

wherein the first transistor is a first charge accumulation control transistor,

wherein the second transistor is a second charge accumulation control transistor,

wherein the third transistor is an amplifying transistor, and

wherein the fourth transistor is an output selection transistor.

9. The semiconductor device according to claim 7,

wherein the first transistor and the second transistor each comprise an oxide semiconductor layer comprising a channel formation region

10. The semiconductor device according to claim 9,

wherein a carrier concentration of the oxide semiconductor layer is lower than 1×

10¹⁴/cm³.

11. The semiconductor device according to claim 7,

wherein the third transistor comprises a semiconductor layer comprising a channel formation region comprising a semiconductor element belonging to Group 14 in the periodic table.

12. The semiconductor device according to claim 7,

wherein the pixel portion comprises a liquid crystal element.

13. A semiconductor device comprising:

a pixel portion configured to display an image, the pixel portion comprising;

a first photoelectric conversion element;

a second photoelectric conversion element;

a first transistor;

a second transistor;

a third transistor;

a fourth transistor; and

a fifth transistor,

wherein the first photoelectric conversion element is electrically connected to one of a source and a drain of the first transistor,

wherein the second photoelectric conversion element is electrically connected to one of a source and a drain of the second transistor,

wherein the other of the source and the drain of the first transistor is electrically connected to a gate of the third transistor,

wherein the other of the source and the drain of the second transistor is electrically connected to the gate of the third transistor,

wherein one of a source and a drain of the third transistor is electrically connected to one of a source and a drain of the fourth transistor, and

wherein one of a source and a drain of the fifth transistor is electrically connected to the gate of the third transistor.

14. The semiconductor device according to claim 13,

wherein the first transistor is a first charge accumulation control transistor,

wherein the second transistor is a second charge accumulation control transistor,

wherein the third transistor is an amplifying transistor,

wherein the fourth transistor is an output selection transistor, and

wherein the fifth transistor is a photodetection reset transistor.

15. The semiconductor device according to claim 13,

wherein the first transistor and the second transistor each comprise an oxide semiconductor layer comprising a channel formation region

16. The semiconductor device according to claim 15,

wherein a carrier concentration of the oxide semiconductor layer is lower than 1×

10¹⁴/cm³.

17. The semiconductor device according to claim 13,

wherein the third transistor comprises a semiconductor layer comprising a channel formation region comprising a semiconductor element belonging to Group 14 in the periodic table.

18. The semiconductor device according to claim 13,

wherein the pixel portion comprises a liquid crystal element.

19. A semiconductor device comprising:

a pixel portion configured to display an image, the pixel portion comprising;

a first photoelectric conversion element;

a second photoelectric conversion element;

a first transistor;

a second transistor;

a third transistor; and

a fourth transistor,

wherein the first photoelectric conversion element is electrically connected to one of a source and a drain of the first transistor,

wherein the second photoelectric conversion element is electrically connected to one of a source and a drain of the second transistor,

wherein the other of the source and the drain of the first transistor is electrically connected to a gate of the third transistor,

wherein the other of the source and the drain of the second transistor is electrically connected to the gate of the third transistor, and

wherein one of a source and a drain of the fourth transistor is electrically connected to the gate of the third transistor.

20. The semiconductor device according to claim 19,

wherein the first transistor is a first charge accumulation control transistor,

wherein the second transistor is a second charge accumulation control transistor,

wherein the third transistor is an amplifying transistor, and

wherein the fourth transistor is a photodetection reset transistor.

21. The semiconductor device according to claim 19,

wherein the first transistor and the second transistor each comprise an oxide semiconductor layer comprising a channel formation region

22. The semiconductor device according to claim 21,

wherein a carrier concentration of the oxide semiconductor layer is lower than 1×

10¹⁴/cm³.

23. The semiconductor device according to claim 19,

wherein the third transistor comprises a semiconductor layer comprising a channel formation region comprising a semiconductor element belonging to Group 14 in the periodic table.

24. The semiconductor device according to claim 19,

wherein the pixel portion comprises a liquid crystal element.