MULTIPLE BITCELLS TRACKING SCHEME FOR SEMICONDUCTOR MEMORIES

• US 20120051160A1
• Filed: 08/26/2010
• Published: 03/01/2012
• Est. Priority Date: 08/26/2010
• Status: Active Grant

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Inventors: TAO, Derek C., LUM, Annie-Li-Keow, LU, Chung-Ji
• Granted Patent: US 8,300,491 B2
• Time in Patent Office: Days
• US Class Current: 365/191
• CPC Class Codes: G11C 11/41 forming static cells with positive feedback, i.e. cells not needing refreshing or charge regeneration, e.g. bistable multivibrator or Schmitt trigger
• CPC Class Codes: G11C 29/50012 of timing

Abstract

A semiconductor memory segment includes a first memory bank having a first tracking cell disposed in a first tracking column. A second memory bank includes a second tracking cell disposed in a second tracking column. A first tracking circuit is coupled to the first and second tracking cells and is configured to output a first signal to memory control circuitry when the first and second tracking cells are accessed. The memory control circuitry is configured to set a clock based on the first signal.

Claims

1. A semiconductor memory, comprising:

a first segment including;

a first memory bank comprising a first plurality of memory cells arranged in rows and columns and a first tracking cell disposed in a first tracking column,

a second memory bank comprising a second plurality of memory cells arranged in rows and columns and a second tracking cell disposed in a second tracking column, and

a first tracking circuit coupled to the first and second tracking cells and configured to output a first signal to memory control circuitry when the first and second tracking cells are accessed;

wherein the memory control circuitry is configured to set a memory clock based on the first signal.

2. The semiconductor memory of claim 1, wherein the first tracking circuit includes a NOR gate coupled to the first tracking column and to the second tracking column.

3. The semiconductor memory of claim 2, wherein the NOR gate of the first tracking circuit has a first input coupled to a first tracking read bit line and a second input coupled to a second tracking read bit line, the first tracking read bit line coupled to the first tracking cell and the second tracking read bit line coupled to the second tracking cell.

4. The semiconductor memory of claim 1, wherein the first memory bank includes a third tracking cell disposed in a third tracking column, and the second memory bank includes a fourth tracking cell disposed in a fourth tracking column.

5. The semiconductor memory of claim 4, further comprising:

a second local tracking circuit coupled to the third and fourth tracking cells, the second tracking circuit configured to output a second signal to the memory control circuitry when the third and fourth tracking cells are accessed;

a second segment including;

a third memory bank comprising a third plurality of memory cells, a fifth tracking cell disposed in a fifth tracking column, and a sixth tracking cell disposed in a sixth tracking column,

a fourth memory bank comprising a fourth plurality of memory cells, a seventh tracking column including a seventh tracking cell, and an eighth tracking column including an eighth tracking cell,

a third tracking circuit coupled to the fifth and seventh tracking cells, the third tracking circuit configured to output a third signal to the memory control circuitry when the fifth and sixth tracking cells have been accessed; and

a fourth tracking circuit coupled to the sixth and eighth tracking cells, the fourth tracking circuit configured to output a fourth signal to the memory control circuitry when the sixth and eighth tracking cells have been accessed.

6. The semiconductor memory array of claim 5, configured to satisfy at least one of the following conditions:

the third tracking column is disposed adjacent to the first tracking column,

the fourth tracking column is disposed adjacent to the second tracking column, and

the sixth tracking column is disposed adjacent to the fifth tracking column,

7. The semiconductor memory of claim 5, wherein each of the tracking circuits includes a NOR gate coupled to tracking read bit lines.

8. The semiconductor memory of claim 5, wherein the memory control circuitry is configured to set a memory clock based on the first, second, third, and fourth signals.

9. The semiconductor memory of claim 5, wherein the memory control circuitry sets the memory clock based on a last received one of the first, second, third, and fourth signals.

10. The semiconductor memory of claim 1, wherein the first and second tracking columns include memory cells.

11. The semiconductor memory of claim 1, wherein the memory cells and the tracking cells are single-ended.

12. A method, comprising:

starting a tracking clock when a tracking signal is transmitted from a memory control circuit of a semiconductor memory;

using a first voltage from a first tracking cell disposed in a first column of a first segment of the semiconductor memory to control a first tracking read bit line in response to receiving the tracking signal;

using a second voltage from a second tracking cell disposed in a second column of the first segment of the semiconductor memory to control a second tracking read bit line in response to receiving the tracking signal;

outputting a first signal to a tracking global bit line from a first tracking circuit in response to receiving the first and second voltages from the first and second tracking read bit lines; and

generating a first reset signal for triggering a reset of the tracking clock when the first signal is received from the tracking global bit line.

13. The method of claim 12, further comprising:

using a third voltage from a third tracking cell disposed in a third column of a first segment of the SRAM array to control a third tracking read bit line in response to receiving the tracking signal;

using a fourth voltage from a fourth tracking cell disposed in a fourth column of the first segment of the SRAM array to control a fourth tracking read bit line in response to receiving the tracking signal;

outputting a second signal to a second tracking global bit line from a second tracking circuit in response to receiving the third and fourth voltages from the third and fourth tracking read bit lines; and

generating a second reset signal for triggering a reset of the tracking clock when the second signal is received from the second tracking global bit line.

14. The method of claim 13, wherein the tracking clock of the semiconductor memory is reset when a last received one of the first and second reset signals is received at the tracking clock, and a clock of the semiconductor memory is set based on the tracking clock.

15. The method of claim 13, wherein the third column is disposed adjacent to the first column and the fourth column is disposed adjacent to the second column.

16. The method of claim 12, wherein the first and second tracking cells are single ended.

17. The method of claim 12, wherein the first tracking circuit includes a NOR gate having a first input coupled to the first tracking read bit line and a second input coupled to the second tracking read bit line.

18. A semiconductor memory, comprising:

a plurality of segments, each of the plurality of segments including;

first and second banks of memory cells in which the memory cells are arranged in rows and columns,

a local tracking circuit disposed between the first and second banks of memory cells, the local tracking circuit including a NOR gate having a first input coupled to a first tracking read bit line and a second input coupled to a second tracking read bit line, the first tracking read bit line coupled to a first tracking cell disposed in a first column of the first bank, the second tracking read bit line coupled to a second tracking cell disposed in a second column of the second bank,

wherein the NOR gate has an output coupled to a global tracking bit line and is configured to trigger a reset of a tracking clock coupled to the global tracking bit line in response to receiving signals identifying that the first and second tracking cells have been accessed from the first and second tracking read bit lines.

19. The semiconductor memory of claim 18, wherein the first and second tracking cells are single-ended.

20. The semiconductor memory of claim 18, wherein a clock of the semiconductor memory is configured to be set based on a last received one of the reset signals received by the tracking clock.