Load Balancing Scheme In Multiple Channel DRAM Systems

• US 20120054423A1
• Filed: 08/31/2010
• Published: 03/01/2012
• Est. Priority Date: 08/31/2010
• Status: Active Grant

• Current Assignee: Qualcomm, Inc.
• Original Assignee: Qualcomm, Inc.
• Inventors: Wang, Feng, Gu, Shiqun, Kim, Jonghae, Nowak, Matthew Michael
• Granted Patent: US 9,268,720 B2
• Time in Patent Office: Days
• US Class Current: 711/105
• CPC Class Codes: G06F 12/0607 Interleaved addressing
• CPC Class Codes: G06F 13/1642 with request queuing
• CPC Class Codes: G06F 13/1647 with interleaved bank access
• CPC Class Codes: G06F 13/1657 Access to multiple memories
• CPC Class Codes: G06F 2213/0064 Latency reduction in handling transfers

Abstract

A load balancing in a multiple DRAM system comprises interleaving memory data across two or more memory channels. Access to the memory channels is controlled by memory controllers. Bus masters are coupled to the memory controllers via an interconnect system and memory requests are transmitted from the bus masters to the memory controller. If congestion is detected in a memory channel, congestion signals are generated and transmitted to the bus masters. Memory requests are accordingly withdrawn or rerouted to less congested memory channels based on the congestion signals.

Claims

1. A method for load balancing in a multiple channel Dynamic Random Access Memory (DRAM) system, the method comprising:

interleaving memory data across two or more memory channels;

controlling access to the memory channels with memory controllers;

coupling bus masters to the memory controllers via an interconnect system;

transmitting memory requests from the bus masters to the memory controllers;

detecting congestion in a first memory channel in response to a memory request to a first memory controller;

generating a congestion signal for the first memory channel; and

transmitting the congestion signal to the bus masters.

2. The method of claim 1, wherein detecting congestion in a first memory channel in response to a memory request comprises tracking outstanding memory requests to the first memory controller, and detecting congestion if a predetermined threshold number of outstanding memory requests is exceeded.

3. The method of claim 1, wherein the congestion signal comprises a single binary bit to represent congestion.

4. The method of claim 1, wherein the congestion signal comprises two or more binary bits to represent a range of congestion levels.

5. The method of claim 1, further comprising withdrawing the memory request to the first memory controller in response to the congestion signal.

6. The method of claim 1, further comprising rerouting the memory request to a second memory controller in response to the congestion signal.

7. The method of claim 1, wherein the DRAM system is integrated in at least one semiconductor die.

8. The method of claim 1, wherein the DRAM system is integrated into a device, selected from the group consisting of a set top box, music player, video player, entertainment unit, navigation device, communications device, personal digital assistant (PDA), fixed location data unit, and a computer.

9. A multiple channel Dynamic Random Access Memory (DRAM) system comprising:

memory data interleaved across two or more memory channels;

memory controllers for controlling access to the memory channels;

bus masters coupled to the memory controllers via an interconnect system, wherein the bus masters are configured to transmit memory requests to the memory controllers; and

logic for generating a congestion signal for a first memory channel coupled to a first memory controller in response to a memory request.

10. The DRAM system of claim 9, wherein logic for generating a congestion signal comprises logic for tracking outstanding memory requests to the first memory controller and generating a congestion signal if a predetermined threshold number of outstanding memory requests is exceeded.

11. The DRAM system of claim 9, wherein the congestion signal comprises a single binary bit to indicate congestion.

12. The DRAM system of claim 9, wherein the congestion signal comprises two or more binary bits to indicate a range of congestion levels.

13. The DRAM system of claim 9 further comprising logic for transmitting the congestion signal to the bus masters.

14. The DRAM system of claim 13, further comprising logic to withdraw the memory request to the first memory controller, in response to the congestion signal.

15. The DRAM system of claim 13, further comprising logic to reroute the memory request to a second memory controller, in response to the congestion signal.

16. The DRAM system of claim 9 integrated in at least one semiconductor die.

17. The DRAM system of claim 9 integrated into a device, selected from the group consisting of a set top box, music player, video player, entertainment unit, navigation device, communications device, personal digital assistant (PDA), fixed location data unit, and a computer.

18. A multiple channel Dynamic Random Access Memory (DRAM) system comprising:

channel means for accessing memory data;

means for interleaving the memory data across two or more channel means;

controller means for controlling access to the channel means;

means for coupling bus masters to the controller means via an interconnect means;

means for transmitting memory requests from the bus masters to the controller means; and

means for generating a congestion indication for a first channel means coupled a first controller means, in response to a memory request.

19. The DRAM system of claim 18, wherein means for generating a congestion signal comprises means for tracking outstanding memory requests to the first controller means, and means for generating the congestion signal if a predetermined threshold number of outstanding memory requests is exceeded.

20. The DRAM system of claim 18, wherein the congestion indication comprises binary signal means for indicating congestion.

21. The DRAM system of claim 18, wherein the congestion indication comprises binary signal means to indicate a range of congestion levels.

22. The DRAM system of claim 18, further comprising means for transmitting the congestion indication to the bus masters.

23. The DRAM system of claim 22, further comprising means for withdrawing the memory request to the first controller means, in response to the congestion indication.

24. The DRAM system of claim 22, further comprising means for rerouting the memory request to a second controller means in response to the congestion indication.

25. The DRAM system of claim 18 integrated in at least one semiconductor die.

26. The DRAM system of claim 18 integrated into a device, selected from the group consisting of a set top box, music player, video player, entertainment unit, navigation device, communications device, personal digital assistant (PDA), fixed location data unit, and a computer.

27. A method for load balancing in a multiple channel Dynamic Random Access Memory (DRAM) system, the method comprising:

step for interleaving memory data across two or more memory channels;

step for controlling access to the memory channels with memory controllers;

step for coupling bus masters to the memory controllers via an interconnect system;

step for transmitting memory requests from the bus masters to the memory controllers;

step for detecting congestion in a first memory channel in response to a memory request to a first memory controller;

step for generating a congestion signal for the first memory channel; and

step for transmitting the congestion signal to the bus masters.

28. The method of claim 27, wherein step for detecting congestion in a first memory channel in response to a memory request comprises step for tracking outstanding memory requests to the first memory controller, and step for detecting congestion if a predetermined threshold number of outstanding memory requests is exceeded.

29. The method of claim 27, wherein the congestion signal comprises a single binary bit to represent congestion.

30. The method of claim 27, wherein the congestion signal comprises two or more binary bits to represent a range of congestion levels.

31. The method of claim 27, further comprising step for withdrawing the memory request to the first memory controller in response to the congestion signal.

32. The method of claim 27, further comprising step for rerouting the memory request to a second memory controller in response to the congestion signal.

33. The method of claim 27, wherein the DRAM system is integrated in at least one semiconductor die.

34. The method of claim 27, wherein the DRAM system is integrated into a device, selected from the group consisting of a set top box, music player, video player, entertainment unit, navigation device, communications device, personal digital assistant (PDA), fixed location data unit, and a computer.