INTELLIGENT POWER CONTROLLER

• US 20120054511A1
• Filed: 08/31/2010
• Published: 03/01/2012
• Est. Priority Date: 08/31/2010
• Status: Active Grant

• Current Assignee: META Platforms Technologies LLC (Meta Platforms, Inc. (f/k/a Facebook, Inc.))
• Original Assignee: Sonics Incorporated (Meta Platforms, Inc. (f/k/a Facebook, Inc.))
• Inventors: Brinks, Ray, de Lescure, Benoit
• Granted Patent: US 8,601,288 B2
• Time in Patent Office: Days
• US Class Current: 713/310
• CPC Class Codes: G06F 1/26 Power supply means, e.g. regulation thereof for memories G11C
• CPC Class Codes: G06F 1/324 by lowering clock frequency
• CPC Class Codes: G06F 1/3243 Power saving in microcontroller unit
• CPC Class Codes: G06F 1/3287 by switching off individual functional units in the computer system
• CPC Class Codes: G06F 1/3296 by lowering the supply or operating voltage
• CPC Class Codes: Y02D 10/00 Energy efficient computing, e.g. low power processors, power management or thermal management

Abstract

A method, apparatus, and system in which an interconnect for an integrated circuit communicates transactions between one or more initiator Intellectual Property (IP) cores and one or more target IP cores coupled to the interconnect, including a power manager having a hierarchy of two or more layers including a hardware logic portion to control a power consumption of two or more domains in the integrated circuit, where each layer of the power manager performs its own function; wherein the power manager has its own dedicated CPU or dedicated state machine to execute power management instructions; and wherein the power manager controls the power consumption of two or more domains without using a CPU IP core utilized by other IP cores on the integrated circuit to execute power management instructions.

Claims

1. An interconnect for an integrated circuit to communicate transactions between one or more initiator Intellectual Property (IP) cores and one or more target IP cores coupled to the interconnect, comprising:

a power manager having a hierarchy of two or more layers including a hardware logic portion to control a power consumption of two or more domains in the integrated circuit, where each layer of the power manager performs its own function;

wherein the power manager has its own

     1) dedicated CPU,

     2) dedicated state machine or

     3) any combination of the two to execute power management instructions;

wherein the power manager controls the power consumption of two or more domains without using a CPU IP core utilized by other IP cores on the integrated circuit to execute power management instructions.

2. The interconnect of claim 1, wherein each domain of the two or more domains includes one or more components that share 1) voltage, 2) clock, or 3) both voltage and clock operating characteristics and operating states, and the power consumption of the two or more domains is controlled through advanced power management techniques comprising clock gating, clock scaling, voltage scaling, power gating, and any combination of these;

wherein the power manager has a dedicated CPU and the dedicated CPU cooperates with an Operating System dedicated for the power manager; and

wherein the power manager controls the power consumption of two or more domains without an Operation System that interacts with applications on the integrated circuit governing the rest of the CPU cores being utilized to transition components in the power domains into a first power consuming mode and back out of the first power consuming mode into a second power consuming mode.

3. The interconnect of claim 1, further comprising individual domain controllers, comprising hardware logic of the power manager, to transition components in an appropriate domain in the integrated circuit into and out of a desired power consuming mode, and cooperates with a software based power management component including an operating system.

4. The interconnect of claim 3, wherein the individual domain controllers transition one or more components they are monitoring and controlling in the appropriate domain into the desired power consuming mode in generally less than 250 and preferably less than 50 clock cycles and transitions the appropriate domain out of the desired power consuming mode in generally less than 1000 and preferably less than 100 clock cycles.

5. The interconnect of claim 3, wherein each domain controller is configured with conflict resolution logic on how to control a power consumption mode of its domain that includes a shared resource by the IP cores of the integrated circuit when one or more power management policies being implemented overlap to control the power consumption mode of the shared resource.

6. The interconnect of claim 3, further comprising a set of one or more activity detector logic units for each domain controller, which feed dynamic signals of whether activity is occurring for one or more components in that domain, wherein the activity detector monitors an communication interface into that domain to see if activity is occurring at each cycle.

7. The interconnect of claim 1, further comprising an advanced communication protocol between the power manager and two or more domains configured to communicate information between the power manager and a select domain it manages, wherein the advanced communication protocol is bidirectional and includes power related information from the select domain to the power manager and power related commands from the power manager to the select domain, and the power related information includes the state and current activity of the selected domain, where domain logic controllers are configured to detect and manage conflicts between the power related commands from the power manager to the select domain and the power related information indicating current activity of the select domain.

8. The interconnect of claim 1, further comprising one or more activity detectors to detect activity from a particular power domain, where the activity detector is configured to sense and communicate an activity level in the particular power domain, including an IP core, to an upper layer of the power manager, and the upper layer of the power manager includes logic to alter a power consumption state of the particular power domain according to the activity level, a transition time to transition the particular domain into and out of the particular power consumption state, and based on a current power management policy being executed, wherein an amount of domains on the integrated circuit is a configurable parameter set by a chip designer at run time fabrication of the integrated circuit, and each domain has its own domain logic controller as well as activity detector, an amount of hardware instantiated required for a given design is scalable to the configurable parameter set by the chip designer.

9. The interconnect of claim 1, wherein the power manager has logic configured to make decisions regarding powering of a domain based in part on a system software power manager including an operating system but without relying on an external operating software to manage the transitions of components in an appropriate domain in the integrated circuit into and out of a desired power consuming mode, and wherein the power manager has one or more software visible registers, tables, or any combination of both that are programmable, so that its behavior can be changed at run-time to support different chip operating modes.

10. The interconnect of claim 1, wherein the power manager further includes multiple power management policies stored in a table, register, matrix or some combination of the three that indicate which components can be transitioned into different power consuming modes during different chip modes and in relation to other applications running on the integrated circuit at that time, wherein the multiple power management policies can be programmed and or updated by a chip designer at design time, run time, and as well as after fabrication during a lifetime of that integrated circuit.

11. The interconnect of claim 1, further comprising a programmable engine, including a dedicated memory space and computing logic, to execute multiple user programs through one or more state machines in a multi-threaded fashion, wherein each thread describes a particular state machine, and the programmable engine provides support for developing run-time modifiable functions by permitting a user to specify complex power management behavior that does not require external software interaction of a CPU of the integrated circuit, wherein the programmable engine monitors a particular power domain activity and includes logic to automatically turn off power to the particular power domain and all domains that depend from it, if a given level of activity is reached and according to a current policy being executed.

12. The interconnect of claim 1, wherein the hierarchy of the power manager includes at least three layers, each with a separate mission, wherein a top level of the hierarchy includes a policy manager, an intermediate level includes two or more power management policies in which the policy manager selects a power management policy to implement, and a low level comprising operating points that map a desired operating state of a domain to operational voltage and clock frequency values for that domain, where a lower hierarchical level including domain controllers to receive the operation point and transition components in that domain into and out of a desired power consuming mode based on an activity occurring or anticipated to occur in that domain and guidance from a power management policy being implemented.

13. The interconnect of claim 1, wherein the hierarchy of the power manager includes at least three layers, each with a separate mission, wherein a top level of the hierarchy includes a policy manager, an intermediate level includes two or more power management policies in which the policy manager selects a power management policy to implement, and a low level comprising operating points that map a desired operating state of a domain to operational voltage and clock frequency values for that domain, and wherein domain controllers for the domain enforce inter-domain dependencies including controlling transition sequences.

14. The interconnect of claim 1, wherein the hierarchy of the power manager includes at least three layers, wherein a top level of the hierarchy includes a policy manager, an intermediate level includes four or more power management policies in which the policy manager selects a power management policy to implement, and a low level comprising operating points that map a desired operating state of a domain to operational voltage and clock frequency values for that domain, and wherein domain controllers for the domain include one or more activity detectors to determine a current activity level of one or more components of a selected domain, and wherein each domain controller of the power manager further includes power conflict resolution logic to detect and manage conflicts between the power manger policy and the activity occurring in that domain, including an IP core being supplied by the activity detector.

15. The interconnect of claim 1, wherein the hierarchy of the power manager includes a low level having operating points that map a desired operating state of a domain to operational voltage and clock frequency values for that domain, where an operating state hardware is configured to implement various operating points and locally transition a given domain into and out of a power consuming mode consist of asynchronous clocks sources, clock division, clock mux, hardware clock gate, power diverter, signal diverter, power splitter, controllable power regulators, signal splitter, finite state machines, clock, phase lock loops, or any combination of these, in which a selection of a new operating point expressing an intended power state of the given domain given a particular system state and under a given power management policy will automatically transition the given domain to the intended power state by supplying an operation voltage and clock frequency value as determined by the new operating point and controlled by one or more hardware components.

16. The interconnect of claim 1, wherein the hierarchy of the power manager includes a low level having operating points that map a desired operating state of a domain to operational voltage and clock frequency values for that domain, where the operating points are named data structures expressing an intended power state of the domain given a particular system state and under a given power management policy stored in software visible registers, tables, or any combination of both, and the power manager hierarchy further includes a low level hierarchical level including domain controllers to receive software functions in response to a selected operating point and using hardware logic to transition clock and power control values of each domain that result from a change in the selected operating point.

17. The interconnect of claim 1, wherein the hierarchy of the power manager includes an intermediate level that has two or more power management policies in which the policy manager selects a power management policy to implement, where the power management policies are stored in a table, hierarchical table, register, matrix or some combination of the three that map different system operating states to different operating points to improve energy savings for a given policy, wherein the table, register, matrix are programmable, so that its behavior can be changed at run-time to support different chip operating modes so that the power management policies can be programmed and or updated by a chip designer at design time, run time, or after fabrication and by a user during operation.

18. The interconnect of claim 1, wherein the hierarchy of the power manager includes an intermediate level that has two or more power management policies in which the policy manager selects a power management policy to implement, where the power management policies are static descriptions of a mapping between a system state and an operating point, and the operating point is a static description of control values for clock and power distribution networks given a power management policy, and the power manager further includes a policy execution engine to execute the power management policy, and a domain controller to execute the operating point so that the domain controller transitions a selected domain from its current state to a new state as indicated by the operating point mapped from the power management policy executed by the policy execution engine.

19. The interconnect of claim 1, wherein the power manager includes groups of domains representing a first level of operating point specification, in which the groups of domains are hierarchically combined into supergroups that follows a hierarchical organization of the integrated circuit, and the power manger includes a hierarchy of controllers, wherein a local state is made visible to the power manager through a domain controller, and a system state is made visible to the power manager through hardware and software tools, to transition the groups of domains into and out of desired operating states.

20. A machine-readable storage medium that stores instructions, which when executed by a machine causes the machine to generate model representations for the integrated circuit of claim 1, which are used in an Electronic Design Automation process.

21. An interconnect for an integrated circuit to communicate transactions between one or more initiator Intellectual Property (IP) cores and one or more target IP cores coupled to the interconnect, comprising:

a power manager having a hierarchy of two or more layers including a hardware logic portion to control a power consumption of two or more domains in the integrated circuit, where each layer of the power manager performs its own function;

wherein the power manager is configured to control a power consumption of two or more domains and resides underneath the Operation System of the integrated circuit in order to transition components in the power domains into a first power consuming mode and back out of the power consuming mode into a second power consuming mode.

22. A method for an integrated circuit to manage power consumption on the integrated circuit, comprising:

communicating transactions between one or more initiator Intellectual Property (IP) cores and one or more target IP cores coupled to a bus type interconnect, comprising;

controlling a power consumption in the integrated circuit with a power manager having a hierarchy of two or more layers including a hardware logic portion located on the interconnect that controls a power consumption of two or more domains in the integrated circuit, where each layer of the power manager performs its own function; and

controlling the power consumption of two or more domains with the power manager and without using a CPU IP core of the integrated circuit to execute power management instructions from the power manager to control the power consumption of the two or more domains.

23. A method for an integrated circuit to manage power consumption on the integrated circuit, comprising:

communicating transactions between one or more initiator Intellectual Property (IP) cores and one or more target IP cores coupled to a bus type interconnect, comprising;

controlling a power consumption in the integrated circuit with a power manager having a hierarchy of two or more layers including a hardware logic portion located on the interconnect that controls a power consumption of two or more domains in the integrated circuit, where each layer of the power manager performs its own function; and

controlling the power consumption of two or more domains with the power manager and where the power manager resides underneath the Operation System of the integrated circuit in order to transition components in the power domains into a first power consuming mode and back out of the power consuming mode into a second power consuming mode.