METHOD AND SYSTEM FOR CONTROLLING POWER IN A CHIP THROUGH A POWER-PERFORMANCE MONITOR AND CONTROL UNIT
First Claim
1. A system for controlling power and performance in a microprocessor system, comprising:
- a monitoring and control system integrated into a microprocessor system, the monitoring and control system including;
a hierarchical architecture, which includes a plurality of layers, each layer in the hierarchal architecture being responsive to commands from a higher level, the commands providing instructions on operations and power distribution, such that the higher levels provide modes of operation and budgets to lower levels and the lower levels provide feedback to the higher levels to control and manage power usage in the microprocessor system both globally and locally,wherein a highest level in the hierarchy includes an operating system implemented in software, which issues the commands to a global power management and control unit (PMCU) by storing data in a register at the global PMCU.
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Abstract
A system and method for controlling power and performance in a microprocessor system includes a monitoring and control system integrated into a microprocessor system. The monitoring and control system includes a hierarchical architecture having a plurality of layers. Each layer in the hierarchal architecture is responsive to commands from a higher level, and the commands provide instructions on operations and power distribution, such that the higher levels provide modes of operation and budgets to lower levels and the lower levels provide feedback to the higher levels to control and manage power usage in the microprocessor system both globally and locally.
12 Citations
24 Claims
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1. A system for controlling power and performance in a microprocessor system, comprising:
a monitoring and control system integrated into a microprocessor system, the monitoring and control system including; a hierarchical architecture, which includes a plurality of layers, each layer in the hierarchal architecture being responsive to commands from a higher level, the commands providing instructions on operations and power distribution, such that the higher levels provide modes of operation and budgets to lower levels and the lower levels provide feedback to the higher levels to control and manage power usage in the microprocessor system both globally and locally, wherein a highest level in the hierarchy includes an operating system implemented in software, which issues the commands to a global power management and control unit (PMCU) by storing data in a register at the global PMCU. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9)
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10. A system for controlling power and performance in a microprocessor system, comprising:
a monitoring and control system integrated into a microprocessor system, the monitoring and control system including; a hierarchical architecture, which includes a plurality of layers, each layer in the hierarchal architecture being responsive to commands from a higher level which provide instructions on operations and power distribution, wherein a highest level in the hierarchy includes an operating system implemented in software which issues the commands to a global power management and control unit (PMCU) by storing data in a register at the global PMCU, each level in the hierarchical architecture including; a monitor device to monitor one or more of events, activity levels, direct power and temperature levels, within a domain of authority of the monitor device; a direct response mechanism configured to manage at least one of power and performance within a domain of action of the direct response mechanism, using a set of commands native to this domain of action; and a reporting device configured to report on monitored results and actions taken, to a next higher level in the hierarchy, if a next higher level exists. - View Dependent Claims (11, 12, 13, 14, 15, 16)
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17. A method for controlling power and performance on a chip, comprising:
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providing a hierarchical power and monitoring system having a plurality of layers with elements of control at each layer of the hierarchy, each element of control having a distinct domain of action and domain of authority; maintaining one or more of a maximum power of a chip or system within a programmable limit, a peak temperature across monitored regions of the chip or system below a specified limit, and a net throughput performance of the chip or system within the specified constraints of power and temperature, by receiving commands from control elements above in the hierarchy to control elements lower in the hierarchy to initiate specified actions in accordance with reports from control elements lower in the hierarchy, wherein a highest level in the hierarchy includes an operating system implemented in software which issues the commands to a global power management and control unit (PMCU) by storing data in a register at the global PMCU. - View Dependent Claims (18, 19, 20, 21, 22, 23, 24)
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Specification