PSEUDO BURIED LAYER AND MANUFACTURING METHOD OF THE SAME, DEEP HOLE CONTACT AND BIPOLAR TRANSISTOR

• US 20120056247A1
• Filed: 09/07/2011
• Published: 03/08/2012
• Est. Priority Date: 09/08/2010
• Status: Active Grant

• Current Assignee: Shanghai Huahong Grace Semiconductor Manufacturing Corporation (Hua Hong Semiconductor Limited)
• Original Assignee: Shanghai Huahong Grace Semiconductor Manufacturing Corporation (Hua Hong Semiconductor Limited)
• Inventors: Liu, Donghua, Qian, Wensheng
• Granted Patent: US 8,592,870 B2
• Time in Patent Office: Days
• US Class Current: 257/197
• CPC Class Codes: H01L 21/28525 the conductive layers comprising semiconducting material H01L21/28518, H01L21/28537 take precedence
• CPC Class Codes: H01L 21/7684 Smoothing; Planarisation
• CPC Class Codes: H01L 29/0657 characterised by the shape of the body
• CPC Class Codes: H01L 29/0821 Collector regions of bipolar transistors
• CPC Class Codes: H01L 29/41708 Emitter or collector electrodes for bipolar transistors
• CPC Class Codes: H01L 29/456 on silicon
• CPC Class Codes: H01L 29/66242 Heterojunction transistors [HBT] with an active layer made of a group 13/15 material H01L29/66318
• CPC Class Codes: H01L 29/7378 comprising lattice mismatched active layers, e.g. SiGe strained layer transistors

Abstract

The present invention discloses a pseudo buried layer, a deep hole contact and a bipolar transistor, and also discloses a manufacturing method of a pseudo buried layer, including: etching a silicon substrate to form an active region and shallow trenches; sequentially implanting phosphorous ion and arsenic ion into the bottom of the shallow trenches to form phosphorus impurity regions and arsenic impurity regions; conducting thermal annealing to the phosphorus impurity regions and arsenic impurity regions. The implantation of the pseudo buried layer, adopting phosphorous with rapid thermal diffusion and arsenic with slow thermal diffusion, can improve the impurity concentration on the surface of the pseudo buried layers, reduce the sheet resistance of the pseudo buried layer, form a good ohmic contact between the pseudo buried layer and a deep hole and reduce the contact resistance, and improve the frequency characteristic and current output of triode devices.

Claims

1. A manufacturing method of pseudo buried layers, comprising the following steps:

step 1;

etching a silicon substrate to form an active region and shallow trenches;

step 2;

implanting phosphorous ion into the bottom of the shallow trenches to form phosphorus impurity regions;

step 3;

implanting arsenic ion into the bottom of the shallow trenches to form arsenic impurity regions;

step 4;

conducting thermal annealing to the phosphorus impurity regions and the arsenic impurity regions.

2. The manufacturing method of pseudo buried layers according to claim 1, wherein, the dosage of the phosphorous ion implantation is 1e14 cm⁻

2˜

1e16 cm<sup>−

2</sup> and the implantation energy is 3 keV˜

30 keV in step 2;

the dosage of the arsenic ion implantation is 1e15 cm<sup>−

2</sup>˜

1e16 cm<sup>−

2</sup> and the implantation energy is 5 keV˜

30 keV in step 3.

3. The manufacturing method of pseudo buried layers according to claim 1, wherein, the diffusion rate of phosphorous ions is higher than that of arsenic ions during the thermal annealing process in step 4, and after the thermal annealing process, the phosphorus impurity regions have a larger coverage area than that of the arsenic impurity regions;

the arsenic impurity regions are retained at the bottom of the shallow trenches;

the phosphorus impurity regions extend laterally into the active region and vertically into the silicon substrate away from the bottom of the shallow trenches; and

the concentration of the arsenic impurity regions is larger than that of the phosphorus impurity regions.

4. A pseudo buried layer, which is formed at the bottom of a shallow trench in a silicon substrate, comprising a phosphorus impurity region and an arsenic impurity region;

wherein, the phosphorus impurity region has a larger coverage area than the arsenic impurity region;

the arsenic impurity region is formed at the bottom of the shallow trench;

the phosphorus impurity region extends laterally into an active region and vertically into the silicon substrate away from the bottom of the shallow trench; and

the concentration of the arsenic impurity region is larger than that of the phosphorus impurity region.

5. The pseudo buried layer according to claim 4, wherein, the phosphorus impurity region is formed through phosphorus ion implantation into the bottom of the shallow trench and thermal annealing thereafter, and the arsenic impurity region is formed through arsenic ion implantation into the bottom of the shallow trench and thermal annealing thereafter.

6. The pseudo buried layer according to claim 5, wherein, the dosage of the phosphorous ion implantation is 1e14 cm⁻

2˜

1e16 cm<sup>−

2</sup> and the implantation energy is 3 keV˜

30 keV;

the dosage of arsenic ion implantation is 1e15 cm<sup>−

2</sup>˜

1e16 cm² and the implantation energy is 5 keV˜

30 keV.

7. A deep hole contact, comprising a metal formed in a deep hole and contacting with a pseudo buried layer, wherein, the deep hole is formed in a shallow trench field oxide on the top of the pseudo buried layer;

the pseudo buried layer is formed at the bottom of a shallow trench in a silicon substrate and comprises a phosphorus impurity region and an arsenic impurity region;

the phosphorus impurity region has a larger coverage area than the arsenic impurity region;

the arsenic impurity region is formed at the bottom of the shallow trench;

the phosphorus impurity region extends laterally into an active region and vertically into the silicon substrate away from the bottom of the shallow trench;

the concentration of the arsenic impurity region is larger than that of the phosphorus impurity region;

an ohmic contact is formed between the metal in the deep hole and the arsenic impurity region.

8. The deep hole contact according to claim 7, wherein, the phosphorus impurity region is formed through phosphorus ion implantation into the bottom of the shallow trench and thermal annealing thereafter, and the arsenic impurity region is formed through arsenic ion implantation into the bottom of the shallow trench and thermal annealing thereafter.

9. The deep hole contact according to claim 8, wherein, the dosage of the phosphorous ion implantation is 1e14 cm⁻

2˜

1e16 cm<sup>−

2</sup> and the implantation energy is 3 keV˜

30 keV;

the dosage of arsenic ion implantation is 1e15 cm<sup>−

2</sup>˜

1e16 cm<sup>−

2</sup> and the implantation energy is 5 keV˜

30 keV.

10. The deep hole contact according to claim 7, the metal in the deep hole comprising a Ti/TiN barrier metal layer and tungsten, wherein, the Ti/TiN barrier metal layer is formed on the inside wall and bottom of the deep hole, and the tungsten is formed on the Ti/TiN barrier metal layer and fills the deep hole.

11. A bipolar transistor, whose N-type region is formed in an active region in a silicon substrate and connects to pseudo buried layers and is picked up through deep hole contacts, wherein, the pseudo buried layers are formed in the silicon substrate at the bottom of shallow trenches adjacent to the active region and each comprises a phosphorus impurity region and an arsenic impurity region;

the coverage area of the phosphorus impurity region is larger than that of the arsenic impurity region;

the arsenic impurity region is formed at the bottom of the respective shallow trench;

the phosphorus impurity region extends laterally into the active region and vertically into the silicon substrate away from the bottom of the respective shallow trench;

the concentration of the arsenic impurity region is larger than that of the phosphorus impurity region;

the N-type region is connected with the phosphorus impurity regions;

each of the deep hole contacts comprises a metal in a deep hole formed in a shallow trench isolation on the top of the respective pseudo buried layer, the metal in the deep hole contacts with the respective pseudo buried layer, and the metal forms an ohmic contact with the respective arsenic impurity region.

12. The bipolar transistor according to claim 11, wherein, the phosphorus impurity region is formed through phosphorus ion implantation into the bottom of the shallow trench and thermal annealing thereafter, and the arsenic impurity region is formed through arsenic ion implantation into the bottom of the shallow trench and thermal annealing thereafter.

13. The bipolar transistor according to claim 12, wherein, the dosage of the phosphorous ion implantation is 1e14 cm⁻

2˜

1e16 cm<sup>−

2</sup> and the implantation energy is 3 keV˜

30 keV;

the dosage of arsenic ion implantation is 1e15 cm<sup>−

2</sup>˜

1e16 cm<sup>−

2</sup> and the implantation energy is 5 keV˜

30 keV.

14. The bipolar transistor according to claim 11, wherein the device is a SiGe NPN heterojunction transistor, whose collector region being the N-type region.