LEVEL SHIFTER

• US 20120056656A1
• Filed: 09/07/2010
• Published: 03/08/2012
• Est. Priority Date: 09/07/2010
• Status: Active Grant

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Inventors: CHEN, Yen-Huei
• Granted Patent: US 8,258,848 B2
• Time in Patent Office: Days
• US Class Current: 327/333
• CPC Class Codes: H03K 3/35613 the input circuit having a differential configuration

Abstract

A level shifter includes first and second NMOS transistors with gates connected to inverted circuit and circuit inputs, respectively, sources connected to the ground, and drains connected to circuit and inverted circuit outputs, respectively. First and second PMOS transistors have their gates connected to the inverted circuit and circuit outputs, respectively, and sources connected to the high voltage supply. A third PMOS transistor of the multiple independent gate type has its source connected to the drain of the first PMOS transistor, drain and back-gate connected to the circuit output, and front-gate connected to the inverted circuit input. A fourth PMOS transistor of the multiple independent gate type has its source connected to the drain of the second PMOS transistor, drain and back-gate connected to the inverted circuit output, and front-gate connected to the circuit input.

Claims

1. A level shifting circuit comprising:

a circuit input that swings between a low voltage supply and ground;

a circuit output that swings between a high voltage supply and the ground;

an inverter with an inverter input connected to the circuit input and an inverter output forming an inverted circuit input;

a first NMOS transistor with gate connected to the inverted circuit input, with source connected to the ground, and with drain connected to the circuit output;

a second NMOS transistor with gate connected to the circuit input and with source connected to the ground;

a first PMOS transistor with gate connected to the second NMOS transistor drain and with source connected to the high voltage supply;

a second PMOS transistor with gate connected to the circuit output and with source connected to the high voltage supply;

a third PMOS transistor, the third PMOS transistor being of the multiple independent gate type, with source connected to the drain of the first PMOS transistor, with drain and back-gate connected to the circuit output, and with front-gate connected to the inverted circuit input; and

a fourth PMOS transistor, the fourth PMOS transistor being of the multiple independent gate type, with source connected to the drain of the second PMOS transistor, with drain and back-gate connected to the second NMOS transistor drain, and with front-gate connected to the circuit input.

2. The circuit of claim 1, wherein the inverter comprises a NMOS transistor and a PMOS transistor.

3. The circuit according to claim 2, wherein said NMOS transistor and said PMOS transistor are low voltage transistors.

4. The circuit according to claim 1, wherein said first and second NMOS transistors and said first, second, third and fourth PMOS transistors are high voltage transistors.

5. The circuit of claim 1, wherein the low voltage supply is less than 0.8 V.

6. The circuit of claim 1, wherein the low voltage supply is less than or equal to about 0.6 V.

7. The circuit according to claim 1, wherein said high voltage supply is greater than or equal to about 1.0 V.

8. The circuit according to claim 1, wherein said high voltage supply is greater than or equal to about 1.2 V.

9. The circuit according to claim 1, further comprising an inverted circuit output connected to the drain of the second NMOS transistor that swings between a high voltage supply and the ground.

10. The circuit according to claim 1, wherein a difference between the low and high voltage supplies is greater than 0.4 V.

11. The circuit according to claim 1, wherein a difference between the low and high voltage supplies is greater than or equal to about 0.55 V.

20. The circuit according to claim 1, wherein a difference between the low and high voltage supplies is greater than or equal to about 0.55 V.

12. A level shifting circuit comprising:

a circuit input that swings between a low voltage supply and ground;

a circuit output that swings between a high voltage supply and the ground;

an inverted circuit output;

an inverter with an inverter input connected to the circuit input and an inverter output forming an inverted circuit input;

a first NMOS transistor with gate connected to the inverted circuit input, with source connected to the ground, and with drain connected to the circuit output;

a second NMOS transistor with gate connected to the circuit input, with source connected to the ground, and with drain connected to the inverted circuit output;

a first PMOS transistor with gate connected to the inverted circuit output and with source connected to the high voltage supply;

a second PMOS transistor with gate connected to the circuit output and with source connected to the high voltage supply;

a third PMOS transistor, the third PMOS transistor being of the double independent gate type, with source connected to the drain of the first PMOS transistor, with drain and back-gate connected to the circuit output, and with front-gate connected to the inverted circuit input; and

a fourth PMOS transistor, the fourth PMOS transistor being of the double independent gate type, with source connected to the drain of the second PMOS transistor, with drain and back-gate connected to the inverted circuit output, and with front-gate connected to the circuit input.

13. The circuit of claim 12, wherein the inverter comprises low voltage devices.

14. The circuit according to claim 13, wherein said first and second NMOS transistors and said first, second, third and fourth PMOS transistors are high voltage transistors.

15. The circuit of claim 12, wherein the low voltage supply is less than 0.8 V.

16. The circuit of claim 12, wherein the low voltage supply is less than or equal to about 0.6 V.

17. The circuit according to claim 16, wherein said high voltage supply is greater than or equal to about 1.0 V.

18. The circuit according to claim 16, wherein said high voltage supply is greater than or equal to about V.

19. The circuit according to claim 12, wherein a difference between the low and high voltage supplies is greater than 0.4 V.