METHOD AND SYSTEM FOR TIME TO DIGITAL CONVERSION WITH CALIBRATION AND CORRECTION LOOPS

• US 20120056769A1
• Filed: 09/02/2010
• Published: 03/08/2012
• Est. Priority Date: 09/02/2010
• Status: Active Grant

• Current Assignee: National Taiwan University (Government of The Republic of China), Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Inventors: WANG, You-Jen, LIU, Shen-Iuan, KUO, Feng Wei, JOU, Chewn-Pu, HSUEH, Fu-Lung
• Granted Patent: US 8,193,963 B2
• Time in Patent Office: Days
• US Class Current: 341/166
• CPC Class Codes: G04F 10/005 Time-to-digital converters [TDC] analog-to-digital converters with intermediate conversion to time or phase H03M1/50, H03M1/60

Abstract

Methods and apparatuses for time to digital conversion (TDC) are disclosed. A timing circuit comprises a TDC circuit, a calibration module, and a correction module. The TDC circuit is configured to provide a timing signal indicative of a timing difference between edges of a periodic reference clock signal and a variable feedback signal. The TDC circuit is also configured to provide a delay signal that is variably delayed relative to the reference clock signal. The calibration module is configured to provide a calibration signal to increase and decrease a total delay of the TDC circuit based on a time delay of the calibration signal plus a time delay of a correction signal. The correction module, which is configured to receive the timing signal and provide the correction signal, minimizes harmonic spurs in a frequency response of the timing signal by operating at a frequency of the reference clock signal.

Claims

1. A timing circuit comprising:

a time to digital conversion (TDC) circuit configured to provide;

a timing signal indicative of a timing difference between edges of a periodic reference clock signal and a first feedback signal, and

a delay signal that is variably delayed relative to the reference clock signal;

a calibration module configured to;

receive the delay signal and a second feedback signal, and

provide a calibration signal to increase and decrease a total delay of the TDC circuit, wherein the total delay of the TDC circuit is based on a time delay of the calibration signal plus a time delay of a correction signal; and

a correction module configured to receive the timing signal and provide the correction signal, the correction module minimizing harmonic spurs in a frequency response of the timing signal by operating at a frequency of the reference clock signal.

2. The timing circuit of claim 1 wherein:

the TDC circuit comprises;

a plurality of latches,

a first delay line, having multiple taps, coupled to the first feedback signal, each tap of the first delay line coupled to a clock input of a corresponding latch,

a second delay line, having multiple taps, coupled to the reference clock signal, each tap of the second delay line coupled to a data input of a corresponding latch, and

an encoder configured to encode outputs from the latches to provide the timing signal;

the calibration module comprises;

a phase detector configured to compare a phase of the delay signal and a phase of the second feedback signal, and

a counter configured to accumulate an output of the phase detector; and

the correction module comprises;

an array of accumulators configured to accumulate values of the timing signal;

an array of comparators coupled to the array of accumulators, each comparator configured to compare one of a plurality of P-bit constant values with an output from a corresponding accumulator; and

an array of registers configured to accumulate and store outputs from the comparators.

3. The timing circuit of claim 2 wherein the phase detector comprises a latch having a data input coupled to the delay signal and a clock input coupled to the second feedback signal.

4. The timing circuit of claim 3 wherein each accumulator comprises:

a first P-bit adder configured to receive one of the P-bit constant values as a first input and the timing signal as a second input;

at least one logic gate configured to receive P input signals from an output of the first P-bit adder;

a second P-bit adder configured to receive an output of the at least one logic gate as a first input; and

a latch configured to;

receive a P-bit output from the adder as a data input and the first feedback signal as a clock input, and

provide a P-bit output signal coupled to a second input of the second P-bit adder.

5. The timing circuit of claim 4 wherein the at least one logic gate effects a NOR logic function.

6. The timing circuit of claim 4 wherein each register comprises:

a P-bit adder configured to receive an output from a corresponding comparator at a first input; and

a latch having a data input coupled to an output of the P-bit adder of the register and having an output coupled to a second input of the P-bit adder of the register.

7. The timing circuit of claim 6 wherein the latches in the TDC circuit, the latch in the phase detector, the latches in the accumulators, and the latches in the registers are D-type flip flops.

8. The timing circuit of claim 7 wherein the TDC circuit comprises 2^P delay cells in the second delay line, and the correction module comprises 2^P accumulators, 2^P comparators, and 2^P registers, each delay cell in the second delay line corresponding to a distinct accumulator, comparator, and register.

9. The timing circuit of claim 8 wherein the correction signal is provided as 2^P individual correction signals, each individual correctional signal provided by a corresponding register and added to the calibration signal to adjust a delay of a corresponding delay cell in the second delay line.

10. The timing circuit of claim 8 wherein a distinct integer between 0 and 2^P−

1, inclusive, is provided as the constant value to each accumulator and to each comparator.

11. The timing circuit of claim 1 wherein the second feedback signal is the first feedback signal shifted in time.

12. The timing circuit of claim 1 wherein the delay signal lags the first feedback signal by one period of the reference clock signal in a calibrated state.

13. The timing circuit of claim 1, further comprising:

a digital loop filter configured to provide a digital control signal based on the timing signal;

a digitally controlled oscillator configured to tune a frequency of an output clock signal based on the digital control signal;

a divider configured to divide the output clock signal in frequency by an integer M or an integer M+1 and provide a divided signal that feeds back to the TDC circuit as the first feedback signal and that feeds back to the calibration module as the second feedback signal; and

a counter configured to accumulate the first feedback signal and provide an increment signal, the increment signal causing the divider to divide by M+1 instead of M in an event that an accumulated sum of the first feedback signal exceeds a predetermined threshold.

14. A method of controlling timing of signals, the method comprising:

receiving a reference clock signal and first and second feedback signals;

delaying the reference clock signal via N delay cells to provide a delay signal;

generating, at a frequency of the reference clock signal, a timing signal indicative of a timing difference between edges of the reference clock signal and of the first feedback signal;

adjusting the delay cells based on the delay signal, the second feedback signal, and the timing signal to calibrate a total delay of the delay cells and to reduce mismatch among delay cells.

15. The method of claim 14 wherein generating the timing signal comprises:

providing delay taps from the delay cells to clock inputs of respective ones of a plurality of latches;

conditionally switching respective latches to delayed values of the first feedback signal; and

encoding, based on outputs from the latches, a position among the latches where outputs of the latches change from a first logic value to a second logic value, to provide the timing signal.

16. The method of claim 14 wherein adjusting the delay cells comprises:

detecting a phase difference between the delay signal and the second feedback signal to provide a phase detection signal;

accumulating the phase detection signal to provide a calibration signal; and

adjusting each delay cell based on the calibration signal.

17. The method of claim 16 wherein adjusting the delay cells further comprises:

accumulating each of N accumulation signals at a corresponding one of N accumulators until a condition based on the timing signal and one of N constant values is met;

comparing the accumulation signals to corresponding constant values to provide N comparison signals;

updating each of N registers based on a corresponding comparison signal to provide N correction signals at outputs of the registers; and

adjusting each delay cell based on the correction signals to compensate for delay cell mismatch.

18. The method of claim 17, wherein adjusting each delay cell comprises:

adding the calibration signal to each of the correction signals to provide N delay update signals; and

updating a delay of each delay cell based on a corresponding delay update signal.

19. The method of claim 17, wherein the condition is that a sum of the constant value and the timing signal is a P-bit digital value having a logical high value at each of P bits, wherein N=2^P.

20. The method of claim 18, further comprising providing a different integer between 0 and N−

1, inclusive, as a corresponding constant value to each accumulator and comparator.

21. The method of claim 16, wherein accumulating the phase detection signal comprises:

incrementing a counter at clock edges specified by the second feedback signal; and

providing an output of the counter as the calibration signal.

22. The method of claim 14, further comprising:

generating a digital control signal based on the timing signal via a low pass filtering operation;

tuning a frequency of an output clock signal based on the digital control signal;

dividing the output clock signal in frequency by an integer M or an integer M+1 to provide a divided signal;

feeding the divided signal back as the first and second feedback signals; and

accumulating the first feedback signal;

wherein the output clock signal is divided in frequency by M+1 in an event the accumulated first feedback signal exceeds a predetermined threshold.