Nonvolatile semiconductor storage device with charge storage layer and its manufacturing method

• US 20120058618A1
• Filed: 10/11/2011
• Published: 03/08/2012
• Est. Priority Date: 03/05/2008
• Status: Active Grant

• Current Assignee: Renesas Electronics Corporation
• Original Assignee: Renesas Electronics Corporation
• Inventors: Hayashi, Fumihiko
• Granted Patent: US 8,298,900 B2
• Time in Patent Office: Days
• US Class Current: 438/287
• CPC Class Codes: H01L 29/40117 the electrodes comprising a charge-trapping insulator
• CPC Class Codes: H01L 29/42344 with at least one additional gate, e.g. program gate, erase gate or select gate
• CPC Class Codes: H01L 29/42348 with trapping site formed by at least two separated sites, e.g. multi-particles trapping site
• CPC Class Codes: H01L 29/792 with charge trapping gate insulator, e.g. MNOS-memory transistors
• CPC Class Codes: H01L 29/7923 Programmable transistors with more than two possible different levels of programmation

Abstract

A method of manufacturing a nonvolatile semiconductor storage device includes sequentially forming a charge storage film, a conductive film, and a mask film on a semiconductor substrate, sequentially removing the mask film, the conductive film, and the charge storage film at a given portion to form a groove, forming a word gate electrode to fill in the groove whose inside is covered with an insulating film, after said forming the word gate electrode, removing the mask film, after said removing the mask film, forming a spacer film to cover the conductive film and the word gate electrode, etching back the spacer film to form a spacer layer on both sides of the word gate electrode through the insulating film, removing the conductive film and the charge storage film to form a control gate electrode, and forming a source drain diffusion layer.

Claims

1. A method of manufacturing a nonvolatile semiconductor storage device, said method comprising:

sequentially forming a charge storage film, a conductive film, and a mask film on a semiconductor substrate;

sequentially removing the mask film, the conductive film, and the charge storage film at a given portion to form a groove;

forming a word gate electrode to fill in the groove whose inside is covered with an insulating film;

after said forming the word gate electrode, removing the mask film;

after said removing the mask film, forming a spacer film to cover the conductive film and the word gate electrode;

etching back the spacer film to form a spacer layer on both sides of the word gate electrode through the insulating film;

removing the conductive film and the charge storage film to form a control gate electrode; and

forming a source drain diffusion layer.

2. The method of claim 1, wherein the charge storage layer includes a laminated film that comprises a silicon oxide film, a silicon nitride film, and a silicon oxide film.

3. The method of claim 1, further comprising:

removing the spacer layer on one of both sides of the word gate electrode before said forming the control gate electrode.

4. The method of claim 1, further comprising:

after said forming the source drain diffusion layer, selectively removing the spacer layer; and

after said selectively removing the spacer layer, turning an upper portion of the word gate electrode, the control gate electrode, and the source drain diffusion layer into silicide.

5. The method of claim 1, wherein in said etching back the spacer film to form the spacer layer, a height of a top surface of the spacer layer, with respect to a bottom surface of the spacer layer, decreases as the top surface of the spacer layer extends farther from the word gate.

6. The method of claim 1, wherein the bottom surface of the spacer layer is located above a top surface of the control gate.

7. The method of claim 1, further comprising:

after said forming the source drain diffusion layer, siliciding an upper portion of the word gate electrode.

8. The method of claim 1, further comprising:

after said forming the source drain diffusion layer, removing the spacer layer.