HYBRID MEMORY MANAGEMENT

• US 20120059992A1
• Filed: 11/14/2011
• Published: 03/08/2012
• Est. Priority Date: 05/28/2008
• Status: Active Grant

• Current Assignee: Round Rock Research LLC
• Original Assignee: Micron Technology, Inc.
• Inventors: Murray, Michael, Furuhjelm, Martin Ragnar, Geldman, John, RADKE, William H.
• Granted Patent: US 8,296,510 B2
• Time in Patent Office: Days
• US Class Current: 711/114
• CPC Class Codes: G06F 12/0246 in block erasable memory, e.g. flash memory
• CPC Class Codes: G06F 2212/1016 Performance improvement
• CPC Class Codes: G06F 2212/1036 Life time enhancement
• CPC Class Codes: G06F 2212/7201 Logical to physical mapping or translation of blocks or pages
• CPC Class Codes: G06F 2212/7211 Wear leveling
• CPC Class Codes: G11C 16/349 Arrangements for evaluating degradation, retention or wearout, e.g. by counting erase cycles
• CPC Class Codes: G11C 2211/5641 Multilevel memory having cells with different number of storage levels

Abstract

Methods and apparatus for managing data storage in hybrid memory devices utilizing single level and multi level memory cells. Logical addresses can be distributed between single level and multilevel memory cells based on a frequency of write operations performed. Initial storage of data corresponding to a logical address in memory can be determined by various methods including initially writing all data to single level memory or initially writing all data to multilevel memory. Other methods permit a host to direct logical address writes to single level or multilevel memory cells based on anticipated usage.

Claims

1. A method for managing data stored on a memory device having a first array of memory cells each memory cell having a first density and a second array of memory cells each memory cell having a second density, comprising:

determining a nature of data to be associated with a logical location in memory;

at least partially based on the nature, storing the data in one of the first array of memory cells and the second array of memory cells.

2. The method of claim 1, wherein the nature of the data is a frequency of usage of the data.

3. The method of claim 1, wherein the nature of the data is at least partially based on if the data is accessed during a particular time frame following power up of the memory device.

4. The method of claim 3, wherein the particular time frame corresponds to a duration of a boot load operation.

5. The method of claim 1, further comprising maintaining at least a particular number of spare locations in the first array of memory cells if locations are available in the second array of memory cells by moving data from the first array of memory cells to the second array of memory cells.

6. The method of claim 1, wherein determining the nature of the data comprises determining an anticipated frequency of usage of the data.

7. The method of claim 1, wherein the first array of memory cells are single level memory cells (SLC) and the second array of memory cells are multi-level memory cells (MLC).

8. The method of claim 1, wherein the first array of memory cells comprises MLC memory cells configured to store a first number of bits per memory cell and the second array of memory cells comprises MLC memory cells configured to store a second number of bits per memory cell, and wherein the second number of bits is greater than the first number of bits.

9. The method of claim 8, further comprising storing data corresponding to file allocation table data in the first array of memory cells.

10. The method of claim 1, further comprising pinning a logical address to one of the first array of memory cells and the second array of memory cells in response to a command provided by the host coupled to the memory device.

11. The method of claim 1, further comprising outputting from the memory device a size of the first array of memory cells and a size of the second array of memory cells in response to a request by the host coupled to the memory device.

12. A method for managing data stored on a memory device having a first array of memory cells each memory cell having a first density and a second array of memory cells each memory cell having a second density, comprising:

determining a nature of data to be associated with a logical location in memory, wherein determining the nature of the data comprises determining whether the data is accessed during a particular time frame following a power up or reset of the memory device; and

at least partially based on the nature, storing the data in one of the first array of memory cells and the second array of memory cells.

13. The method of claim 12, wherein storing the data further comprises storing the data in one of the first array of memory cells and the second array of memory cells where the second density is greater than the first density.

14. The method of claim 13, wherein the data is stored in the first array of memory cells if it is determined that the data is accessed during a particular time frame following reset of the memory device.

15. The method of claim 12, further comprising maintaining at least a particular number of spare locations in the first array of memory cells if locations are available in the second array of memory cells by moving data from the first array of memory cells to the second array of memory cells.

16. A method for managing data stored on a memory device having a first array of memory cells each memory cell having a first density and a second array of memory cells each memory cell having a second density, comprising:

determining a nature of data to be associated with a logical location in memory; and

at least partially based on the nature, storing the data in one of the first array of memory cells and the second array of memory cells;

wherein the nature of the data associated with the logical location corresponds to whether the logical location is accessed during a particular time frame following power up or reset of the memory device;

wherein data associated with a logical location accessed during the particular time frame following power up or reset is stored in the first array of memory cells; and

wherein the second density is greater than the first density.

17. A method for managing data stored on a memory device having a first array of memory cells each memory cell having a first density and a second array of memory cells each memory cell having a second density, comprising:

determining a nature of data to be associated with a logical location in memory, wherein determining a nature of data at least partially comprises determining an anticipated frequency of updates of data associated with the logical location;

at least partially based on the nature, storing the data in one of the first array of memory cells and the second array of memory cells; and

maintaining at least a particular number of spare locations in the first array of memory cells if locations are available in the second array of memory cells by moving data from the first array of memory cells to the second array of memory cells;

wherein the second density is greater than the first density.

18. The method of claim 17, wherein determining a nature of data further comprises determining the nature of the data responsive to an indicator received by the memory device from a host coupled to the memory device.

19. An electronic system comprising:

a host having a hard disk drive interface utilizing a hard disk drive protocol for interfacing with a hard disk drive having solid state memory and magnetic media memory;

a memory device configured to emulate a hard disk drive and coupled to the host at least in part through the hard disk drive interface, the memory device comprising;

a first array of memory cells wherein each memory cell has a first density;

a second array of memory cells wherein each memory cell has a second density; and

control circuitry configured to store data indicated by the host to be stored in the solid state memory of a hard disk drive in the first array of memory cells and store data indicated by the host to be stored in the magnetic media of a hard disk drive in the second array of memory cells;

wherein the first density is less than the second density.

20. The electronic system of claim 19, wherein the first array of memory cells are single level memory cells (SLC) and the second array of memory cells are multi-level memory cells (MLC).

21. The electronic system of claim 19, wherein the first array of memory cells comprises MLC memory cells configured to store a first number of bits per memory cell and the second array of memory cells comprises MLC memory cells configured to store a second number of bits per memory cell, and wherein the second number of bits is greater than the first number of bits.

22. The electronic system of claim 19, wherein the control circuitry is further configured to pin a logical address to one of the first array of memory cells and the second array of memory cells in response to a command provided by the host.

23. The electronic system of claim 19, wherein the control circuitry is further configured to output a size of the first array of memory cells and a size of the second array of memory cells in response to a request by the host.