TRAFFIC CONTROL METHOD AND APPARATUS OF MULTIPROCESSOR SYSTEM

• US 20120060007A1
• Filed: 09/02/2011
• Published: 03/08/2012
• Est. Priority Date: 09/03/2010
• Status: Active Grant

• Current Assignee: Samsung Electronics Co. Ltd.
• Original Assignee: Samsung Electronics Co. Ltd.
• Inventors: LEE, Seung Wook, BAIK, Min Seung, KIM, Joong Baik, KWON, Soon Wan
• Granted Patent: US 8,909,873 B2
• Time in Patent Office: Days
• US Class Current: 711/163
• CPC Class Codes: G06F 15/17325 Synchronisation; Hardware support therefor intertask synchronisation G06F9/52

Abstract

A method and apparatus for controlling traffic of multiprocessor system or multi-core system is provided. The traffic control apparatus of a multiprocessor system according to the present invention includes a request handler for processing a traffic request of a first processor, and a Quality of Service (QoS) manager for receiving a QoS guaranty start instruction for a second processor from the multiprocessor system, and for transmitting, when traffic of the second processor is detected, a traffic adjustment signal to the request handler. The request handler adjusts the traffic of the first processor according to the received traffic adjustment signal. The traffic control method and apparatus of the present invention is capable of adjusting the required bandwidths of individual technologies and guaranteeing the real-timeness in the multiprocessor system or multi-core system.

Claims

1. A traffic control apparatus of a multiprocessor system, the apparatus comprising:

a request handler for processing a traffic request of a first processor; and

a Quality of Service (QoS) manager for receiving a QoS guaranty start instruction for a second processor from the multiprocessor system, and for transmitting, when traffic of the second processor is detected, a traffic adjustment signal to the request handler,

wherein the request handler adjusts the traffic of the first processor according to the traffic adjustment signal.

2. The apparatus of claim 1, wherein the QoS manager transmits, when a QoS scenario identifier and a QoS level identifier are received from the multiprocessor system, the traffic adjustment signal instructing to adjust the traffic in a QoS guaranty scheme corresponding to the QoS scenario identifier and the QoS level identifier.

3. The apparatus of claim 2, wherein the request handler analyzes the traffic of the first processor and transmits traffic amount information to the QoS manager, and the QoS manager receives and analyzes, when the QoS scenario identifier and the QoS level identifier are received from the multiprocessor system, the traffic amount information, determines whether QoS level compensation is necessary based on the traffic amount of the first processor, and compensates, when the QoS level compensation is necessary, the QoS level.

4. The apparatus of claim 3, wherein the QoS manager comprises a register and receives the QoS scenario identifier and the QoS level identifier from the multiprocessor system by detecting the QoS scenario identifier and the QoS level identifier registered in the register.

5. The apparatus of claim 1, wherein the QoS manager transmits, when completion of traffic transmission of the second processor is detected, a traffic adjustment release signal to the request handler, and the request handler ends, when the traffic adjustment release signal is received, the adjustment of the traffic of the first processor.

6. The apparatus of claim 1, wherein the QoS manager transmits, when a QoS guaranty end instruction for the second processor is received from the multiprocessor system, a traffic adjustment release signal to the request handler, and the request handler ends, when the traffic adjustment release signal is received, the adjustment of the traffic of the first processor.

7. The apparatus of claim 1, wherein the QoS manager comprises a register and receives a QoS guaranty start instruction and a QoS guaranty end instruction of the second processor from the multiprocessor system by detecting a processor identifier registered in the register.

8. The apparatus of claim 1, wherein the traffic adjustment signal comprises a traffic blocking signal, and the request handler blocks, when the traffic blocking signal is received, the traffic of the first processor.

9. The apparatus of claim 1, wherein the traffic adjustment signal comprises a traffic adjustment method, and further wherein the traffic adjustment method comprises at least one of permitting a predetermined amount of traffic of the first processor and rejecting all traffic of the first processor.

10. The apparatus of claim 1, further comprising a memory,

wherein, the traffic adjustment signal comprises a traffic adjustment method, and further wherein the traffic adjustment method comprises permitting the first processor to read data from the memory and blocking the first processor from writing data to the memory.

11. A traffic control method of a multiprocessor system, the method comprising:

processing, at a request handler, a traffic request of a first processor;

receiving, at a Quality of Service (QoS) manager, a QoS guaranty start instruction for a second processor from the multiprocessor system;

transmitting, when traffic of the second processor is detected, a traffic adjustment signal from the QoS manager to the request handler; and

adjusting, at the request handler, the traffic of the first processor according to the traffic adjustment signal.

12. The method of claim 11, wherein the QoS manager transmits, when a QoS scenario identifier and a QoS level identifier are received from the multiprocessor system, the traffic adjustment signal instructing to adjust the traffic in a QoS guaranty scheme corresponding to the QoS scenario identifier and the QoS level identifier.

13. The method of claim 12, further comprising:

analyzing, at the request handler, the traffic of the first processor;

transmitting traffic amount information from the request handler to the QoS manager;

receiving and analyzing, at the QoS manager when the QoS scenario identifier and the QoS level identifier are received from the multiprocessor system, the traffic amount information;

determining whether QoS level compensation is necessary based on the traffic amount of the first processor; and

compensating, when the QoS level compensation is necessary, the QoS level.

14. The method of claim 13, wherein the QoS manager comprises a register and receives the QoS scenario identifier and the QoS level identifier from the multiprocessor system by detecting the QoS scenario identifier and the QoS level identifier registered in the register.

15. The method of claim 11, further comprising:

transmitting, when completion of traffic transmission of the second processor is detected, a traffic adjustment release signal from the QoS manager to the request handler; and

ending, at the request handler when the traffic adjustment release signal is received, the adjustment of the traffic of the first processor.

16. The method of claim 11, further comprising:

transmitting, when a QoS guaranty end instruction for the second processor is received from the multiprocessor system, a traffic adjustment release signal from the QoS manager to the request handler; and

ending, at the request handler when the traffic adjustment release signal is received, the adjustment of the traffic of the first processor.

17. The method of claim 11, wherein the QoS manager comprises a register and receives a QoS guaranty start instruction and a QoS guaranty end instruction of the second processor from the multiprocessor system by detecting a processor identifier registered in the register.

18. The method of claim 11, wherein the traffic adjustment signal comprises a traffic blocking signal, and the request handler blocks, when the traffic blocking signal is received, the traffic of the first processor.

19. The method of claim 11, wherein the traffic adjustment signal comprises a traffic adjustment method, and further wherein the traffic adjustment method comprises at least one of permitting a predetermined amount of traffic of the first processor and rejecting all traffic of the first processor.

20. The method of claim 11, wherein, the traffic adjustment signal comprises a traffic adjustment method, and further wherein the traffic adjustment method comprises permitting the first processor to read data from a memory and blocking the first processor from writing data to the memory.