METHOD OF PROVIDING A FLEXIBLE SEMICONDUCTOR DEVICE AT HIGH TEMPERATURES AND FLEXIBLE SEMICONDUCTOR DEVICE THEREOF

• US 20120061672A1
• Filed: 11/17/2011
• Published: 03/15/2012
• Est. Priority Date: 12/02/2008
• Status: Active Grant

• Current Assignee: Arizona Board of Regents (University of Arizona)
• Original Assignee: Arizona Board of Regents (University of Arizona)
• Inventors: O'Rourke, Shawn, Ageno, Scott, Marrs, Michael, Moyer, Curtis, Bottesch, Dirk, O'Brien, Barry
• Granted Patent: US 8,999,778 B2
• Time in Patent Office: Days
• US Class Current: 257/57
• CPC Class Codes: H01L 21/6835 using temporarily an auxiliary support
• CPC Class Codes: H01L 2221/6835 used as a support during build up manufacturing of active devices
• CPC Class Codes: H01L 29/66765 Lateral single gate single channel transistors with inverted structure, i.e. the channel layer is formed after the gate
• CPC Class Codes: H01L 29/78603 characterised by the insulating substrate or support H01L29/78657 takes precedence
• CPC Class Codes: H01L 2924/3025 Electromagnetic shielding
• CPC Class Codes: H05K 1/0393 Flexible materials H05K1/038 takes precedence; specific organic compositions are classified in H05K1/0313 and subgroups
• CPC Class Codes: H05K 2201/0145 Polyester, e.g. polyethylene terephthalate [PET], polyethylene naphthalate [PEN]
• CPC Class Codes: H05K 2201/0154 Polyimide
• CPC Class Codes: H05K 2201/068 wherein the coefficient of thermal expansion is important
• CPC Class Codes: H05K 3/007 Manufacture or processing of a substrate for a printed circuit board supported by a temporary or sacrificial carrier H05K1/187, H05K3/20 and H05K3/4682 take precedence

Abstract

Some embodiments include a method of providing a semiconductor device. The method can include: (a) providing a flexible substrate; (b) depositing at least one layer of material over the flexible substrate, wherein the deposition of the at least one layer of material over the flexible substrate occurs at a temperature of at least 180° C.; and (c) providing a diffusion barrier between a metal layer and an a-Si layer. Other embodiments are disclosed in this application.

Claims

1. A method of providing a semiconductor device, the method comprising:

providing a flexible substrate;

depositing at least one layer of material over the flexible substrate, wherein depositing the at least one layer of material over the flexible substrate occurs at a temperature of at least 180°

C.; and

providing a diffusion barrier between a metal layer and an N+ amorphous silicon layer.

2. The method of claim 1, wherein:

depositing the at least one layer of material over the flexible substrate comprises at least one of;

depositing an amorphous silicon layer;

depositing a silicon nitride gate dielectric;

or

depositing a silicon nitride intermetal dielectric layer.

3. The method of claim 1, wherein at least one of:

depositing the at least one layer of material over the flexible substrate occurs at a temperature of at least 188°

C.;

or

depositing the at least one layer of material over the flexible substrate occurs at near vacuum pressure.

4. The method of claim 1, wherein at least one of:

the diffusion barrier comprises tantalum;

or

the flexible substrate comprises polyethylene naphthalate.

5. The method of claim 1, wherein:

the flexible substrate comprises a planarized flexible substrate.

6. The method of claim 1, further comprising:

providing a carrier substrate; and

coupling the carrier substrate to the flexible substrate.

7. The method of claim 1, further comprising:

providing a first dielectric material, wherein the first dielectric material comprises an organic siloxane-based dielectric material.

8. The method of claim 7, further comprising:

providing a second dielectric material, wherein the second dielectric material comprises silicon nitride and is deposited over the first dielectric material; and

baking the first dielectric material, the second dielectric material, the flexible substrate, and the at least one layer of material, wherein the temperature of the baking reaches at least 200°

C.

9. The method of claim 7, wherein:

providing a base dielectric material before providing the first dielectric material, wherein the base dielectric material comprises silicon oxide.

10. A method of providing a semiconductor device, the method comprising:

providing a carrier substrate;

providing a flexible substrate, wherein the flexible substrate is planarized;

coupling the carrier substrate to the flexible substrate;

depositing a gate metal layer over the flexible substrate;

depositing one or more silicon comprising layers over the gate metal layer, wherein the temperature of the depositing the one or more silicon comprising layers reaches at least 180°

C.;

depositing one or more contact elements over the one or more silicon comprising layers, wherein the one or more contact elements comprises a diffusion barrier;

depositing a first dielectric material over the one or more contact elements, wherein the first dielectric material comprises an organic siloxane-based dielectric material;

depositing a second dielectric material over the first dielectric material, wherein the second dielectric material comprises silicon nitride; and

baking the first dielectric material, the second dielectric material, the flexible substrate, the carrier substrate, the gate metal layer, the one or more silicon comprising layers, and the one or more contact elements, wherein the temperature of the baking reaches at least 200°

C.

11. The method of claim 10, wherein:

the one or more silicon comprising layers comprises an amorphous silicon layer.

12. The method of claim 11, wherein:

the one or more silicon comprising layers further comprises a silicon nitride gate dielectric layer and a silicon nitride intermetal dielectric layer.

13. The method of claim 12, further comprising:

etching the silicon nitride intermetal dielectric layer, the amorphous silicon layer, and the silicon nitride gate dielectric layer so that a portion of the amorphous silicon layer is exposed; and

depositing a mesa passivation layer over the silicon nitride intermetal dielectric layer, the amorphous silicon layer, and the silicon nitride gate dielectric layer so that the mesa passivation layer covers the exposed portion of the amorphous silicon layer.

14. The method of claim 10, wherein:

the diffusion barrier comprises tantalum; and

the one or more contact elements further comprises a metal layer and N+ amorphous silicon layer.

15. The method of claim 14, wherein:

depositing one or more contact elements comprises depositing the diffusion barrier between the metal layer and the N+ amorphous silicon layer.

16. The method of claim 15, further comprising:

etching the one or more contact elements, wherein the one or more contact elements are etched in a single process.

17. The method of claim 10, wherein:

depositing one or more one silicon comprising layers comprises using plasma-enhanced chemical vapor deposition.

18. A semiconductor device, the semiconductor device comprising:

a flexible substrate;

a metal gate layer over the flexible substrate;

an amorphous silicon layer over the metal gate layer, wherein the amorphous silicon layer is deposited during a process at a temperature of at least 180°

C.;

an N+ amorphous silicon layer over the amorphous silicon layer;

a diffusion barrier; and

a metal layer;

wherein the diffusion barrier is positioned between the metal layer and the N+ amorphous silicon layer.

19. The semiconductor device of claim 18, wherein at least one of:

the flexible substrate comprises polyethylene naphthalate;

the diffusion barrier comprises tantalum;

or

the metal layer comprises aluminum.

20. The semiconductor device of claim 18, further comprising:

a mesa passivation layer between the amorphous silicon layer and the N+ amorphous silicon layer.