BARRIER LAYER FORMATION FOR METAL INTERCONNECTS THROUGH ENHANCED IMPURITY DIFFUSION

• US 20120061838A1
• Filed: 09/15/2010
• Published: 03/15/2012
• Est. Priority Date: 09/15/2010
• Status: Active Grant

• Current Assignee: Globalfoundries US Incorporated (GlobalFoundries, Inc.)
• Original Assignee: International Business Machines Corporation
• Inventors: Edelstein, Daniel C., Nogami, Takeshi, Shobha, Hosadurga K.
• Granted Patent: US 8,492,289 B2
• Time in Patent Office: Days
• US Class Current: 257/751
• CPC Class Codes: H01L 21/76832 Multiple layers
• CPC Class Codes: H01L 21/76834 formation of thin insulating films on the sidewalls or on top of conductors H01L21/76831 takes precedence
• CPC Class Codes: H01L 21/76849 the layer being positioned on top of the main fill metal
• CPC Class Codes: H01L 21/76864 Thermal treatment
• CPC Class Codes: H01L 21/76867 characterized by methods of formation other than PVD, CVD or deposition from a liquids PVD H01L21/2855; CVD H01L21/28556; deposition from liquids H01L21/288
• CPC Class Codes: H01L 21/76873 for electroplating
• CPC Class Codes: H01L 23/53238 Additional layers associated with copper layers, e.g. adhesion, barrier, cladding layers
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Abstract

A method of forming a barrier layer for metal interconnects of an integrated circuit device includes forming a first cap layer over a top surface of a conductive line of the integrated circuit device in a manner that facilitates a controllable dose of oxygen provided to the top surface of the conductive line, the conductive line comprising a metal formed over a seed layer that is an impurity alloy of the metal; and annealing the integrated circuit device so as to combine diffused impurity atoms of the seed layer with the controllable dose of oxygen, thereby forming an impurity oxide layer at an interface between the first cap layer and the top surface of the conductive line.

Claims

1. A method of forming a barrier layer for metal interconnects of an integrated circuit device, the method comprising:

forming a first cap layer over a top surface of a conductive line of the integrated circuit device in a manner that facilitates a controllable dose of oxygen provided to the top surface of the conductive line, the conductive line comprising a metal formed over a seed layer that is an impurity alloy of the metal; and

annealing the integrated circuit device so as to combine diffused impurity atoms of the seed layer with the controllable dose of oxygen, thereby forming an impurity oxide layer at an interface between the first cap layer and the top surface of the conductive line.

2. The method of claim 1, wherein the first cap layer comprises an oxygen permeable cap layer.

3. The method of claim 2, wherein the first cap layer comprises a nitrogen free cap layer.

4. The method of claim 2, wherein the annealing is performed in an oxygen containing environment.

5. The method of claim 4, further comprising forming a second cap layer over the first cap layer following the annealing.

6. The method of claim 5, wherein the second cap layer comprises an oxygen blocking cap layer.

7. The method of claim 1, wherein oxygen is a constituent element of the first cap layer.

8. The method of claim 7, further comprising forming a second cap layer over the first cap layer prior to the annealing.

9. The method of claim 8, wherein the second cap layer comprises an oxygen blocking cap layer.

10. The method of claim 1, wherein the metal comprises copper (Cu), and the impurity alloy of copper comprises one of more of:

manganese (Mn), aluminum (Al), chromium (Cr) and vanadium (Va).

11. A method of forming a barrier layer for metal interconnects of an integrated circuit device, the method comprising:

forming a conductive line in an insulating layer of the semiconductor device by forming a metal material over a seed layer that is an impurity alloy of the metal;

forming a first cap layer over a top surface of the conductive line, the first cap layer comprising an oxygen permeable cap layer;

annealing the integrated circuit device so as to combine diffused impurity atoms of the seed layer with the controllable dose of oxygen, thereby forming an impurity oxide layer at an interface between the first cap layer and the top surface of the conductive line; and

forming a second cap layer over the first cap layer following the annealing, the second cap layer comprising an oxygen blocking cap layer.

12. The method of claim 11, wherein the oxygen permeable cap layer is a nitrogen free layer comprising one of more of SiC and SiCH.

13. The method of claim 12, wherein the metal comprises copper (Cu), and the impurity alloy of copper comprises one of more of:

manganese (Mn), aluminum (Al), chromium (Cr) and vanadium (Va).

14. The method of claim 13, wherein the oxygen blocking cap layer comprises one of more of SiN and SiCN.

15. The method of claim 11, wherein the annealing is performed at a temperature of about 200°

C. to about 450°

C., and for a duration of about 10 minutes to about 2 hours.

16. A method of forming a barrier layer for metal interconnects of an integrated circuit device, the method comprising:

forming a conductive line in an insulating layer of the semiconductor device by forming a metal material over a seed layer that is an impurity alloy of the metal;

forming a first cap layer over a top surface of the conductive line, wherein oxygen is a constituent element of the first cap layer;

forming a second cap layer over the first cap layer, the second cap layer comprising an oxygen blocking cap layer; and

annealing the integrated circuit device so as to combine diffused impurity atoms of the seed layer with oxygen released by the first cap layer, thereby forming an impurity oxide layer at an interface between the first cap layer and the top surface of the conductive line.

17. The method of claim 16, wherein the first cap layer comprises one or more of SiCOH, SiON, and SiOCNH.

18. The method of claim 16, wherein the second cap layer comprises one of more of SiN and SiCN.

19. The method of claim 16, wherein the metal comprises copper (Cu), and the impurity alloy of copper comprises one of more of:

manganese (Mn), aluminum (Al), chromium (Cr) and vanadium (Va).

20. A metal interconnect structure for an integrated circuit device, comprising:

a first cap layer formed over a top surface of a conductive line of the integrated circuit device to facilitate a controllable dose of oxygen provided to the top surface of the conductive line, the conductive line comprising a metal formed over a seed layer that is an impurity alloy of the metal; and

an impurity oxide layer formed at an interface between the first cap layer and the top surface of the conductive line, the impurity oxide layer formed from diffused impurity atoms of the seed layer combined with the controllable dose of oxygen.

21. The structure of claim 20, wherein the first cap layer comprises an oxygen permeable cap layer.

22. The structure of claim 21, wherein the first cap layer comprises a nitrogen free cap layer.

23. The structure of claim 22, wherein the first cap layer is a nitrogen free layer comprising one of more of SiC and SiCH.

24. The structure of claim 20, further comprising a second cap layer formed over the first cap layer.

25. The structure of claim 24, wherein the second cap layer comprises an oxygen blocking cap layer.

26. The structure of claim 25, wherein the second cap layer comprises one of more of SiN and SiCN.

27. The structure of claim 20, wherein the metal comprises copper (Cu), and the impurity alloy of copper comprises one of more of:

manganese (Mn), aluminum (Al), chromium (Cr) and vanadium (Va).

28. The structure of claim 20, wherein oxygen is a constituent element of the first cap layer.

29. The structure of claim 28, wherein the first cap layer comprises one or more of SiCOH, SiON, and SiOCNH.