SIMULATED WIREBOND SEMICONDUCTOR PACKAGE

• US 20120061851A1
• Filed: 06/07/2010
• Published: 03/15/2012
• Est. Priority Date: 06/16/2009
• Status: Active Grant

• Current Assignee: HSIO Technologies LLC
• Original Assignee: HSIO Technologies LLC
• Inventors: Rathburn, James
• Granted Patent: US 8,981,568 B2
• Time in Patent Office: Days
• US Class Current: 257/774
• CPC Class Codes: B23K 1/0016 Brazing of electronic components
• CPC Class Codes: B23K 20/004 Wire welding
• CPC Class Codes: B23K 2101/42 Printed circuits
• CPC Class Codes: H01L 21/6835 using temporarily an auxiliary support
• CPC Class Codes: H01L 2223/6677 for antenna, e.g. antenna included within housing of semiconductor device
• CPC Class Codes: H01L 2225/06524 Electrical connections formed on device or on substrate, e.g. a deposited or grown layer
• CPC Class Codes: H01L 2225/06568 the devices decreasing in size, e.g. pyramidical stack
• CPC Class Codes: H01L 23/3107 the device being completely enclosed
• CPC Class Codes: H01L 23/48 Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
• CPC Class Codes: H01L 23/552 Protection against radiation, e.g. light or electromagnetic waves
• CPC Class Codes: H01L 24/50 Tape automated bonding [TAB] connectors, i.e. film carriers; Manufacturing methods related thereto thin flexible metallic tape with or without a film carrier H01L23/49572, flexible insulating substrates H01L23/4985, H01L23/5387
• CPC Class Codes: H01L 24/86 using tape automated bonding [TAB]
• CPC Class Codes: H01L 25/0655 the devices being arranged next to each other
• CPC Class Codes: H01L 25/0657 Stacked arrangements of devices
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00012 Relevant to the scope of the group, the symbol of which is combined with the symbol of this group
• CPC Class Codes: H01L 2924/01004 Beryllium [Be]
• CPC Class Codes: H01L 2924/01005 Boron [B]
• CPC Class Codes: H01L 2924/01006 Carbon [C]
• CPC Class Codes: H01L 2924/01013 Aluminum [Al]
• CPC Class Codes: H01L 2924/01015 : Phosphorus [P]
• CPC Class Codes: H01L 2924/01029 : Copper [Cu]
• CPC Class Codes: H01L 2924/01033 : Arsenic [As]
• CPC Class Codes: H01L 2924/01046 : Palladium [Pd]
• CPC Class Codes: H01L 2924/01047 : Silver [Ag]
• CPC Class Codes: H01L 2924/01049 : Indium [In]
• CPC Class Codes: H01L 2924/01075 : Rhenium [Re]
• CPC Class Codes: H01L 2924/01078 : Platinum [Pt]
• CPC Class Codes: H01L 2924/01079 : Gold [Au]
• CPC Class Codes: H01L 2924/01082 : Lead [Pb]
• CPC Class Codes: H01L 2924/014 : Solder alloys
• CPC Class Codes: H01L 2924/09701 : Low temperature co-fired ceramic [LTCC]
• CPC Class Codes: H01L 2924/12044 : OLED
• CPC Class Codes: H01L 2924/1306 : Field-effect transistor [FET]
• CPC Class Codes: H01L 2924/14 : Integrated circuits
• CPC Class Codes: H01L 2924/181 : Encapsulation
• CPC Class Codes: H01L 2924/19041 : being a capacitor
• CPC Class Codes: H01L 2924/19042 : being an inductor
• CPC Class Codes: H01L 2924/19043 : being a resistor
• CPC Class Codes: H01L 2924/30107 : Inductance
• CPC Class Codes: H01L 2924/3011 : Impedance
• CPC Class Codes: H01L 2924/3025 : Electromagnetic shielding

Abstract

A semiconductor package with simulated wirebonds. A substrate is provided with a plurality of first pads on a first surface and a plurality of second pads on a second surface. Each of the first pads are electrically coupled to one or more of the second pads. At least one semiconductor device is located proximate the first surface of a substrate. The simulated wirebonds include at least a first dielectric layer selectively printed to create a plurality of recesses, and a conductive material located in the recesses to form first and second contact pads, and electrical traces electrically coupling the first and second contact pads. The first contact pads are electrically coupled to terminals on the semiconductor device and the second contact pads are electrically coupled to the first pads on the first surface of the substrate. An overmolding material seals the semiconductor device and the simulated wirebonds

Claims

1-32. -32. (canceled)

33. A semiconductor package comprising:

a substrate comprising a plurality of first pads on a first surface and a plurality of second pads on a second surface, each of the first pads electrically coupled to one or more of the second pads;

at least one semiconductor device comprising a first surface located proximate the first surface of a substrate and a second surface with terminals oriented to face away from the first surface of the substrate;

at least one simulated wirebond comprising at least a first dielectric layer selectively printed to create a plurality of recesses, and a conductive material located in the recesses to form first and second contact pads, and electrical traces electrically coupling the first and second contact pads, the first contact pads electrically coupled to the terminals on the semiconductor device and the second contact pads electrically coupled to the first pads on the first surface of the substrate so the simulated wirebond extends from the first surface of the substrate to the second surface of the semiconductor device; and

overmolding material sealing the semiconductor device and the simulated wirebonds to the first surface of the substrate.

34. The semiconductor package of claim 33 comprising a plurality of dielectric layers substantially surrounding the conductive traces.

35. The semiconductor package of claim 33 wherein the conductive traces comprise a circuit geometry that extends beyond electrically coupling the first and second contact pads.

36. The semiconductor package of claim 33 wherein conductive traces comprise substantially rectangular cross-sectional shapes.

37. The semiconductor package of claim 33 wherein the conductive traces comprises one of sintered conductive particles or a conductive ink.

38. The semiconductor package of claim 33 comprising a compliant material located between the second contact pads and the overmolding material.

39. The semiconductor package of claim 33 comprising at least one electrical device printed on one of the dielectric layers and electrically coupled to at least one of the conductive traces.

40. The semiconductor package of claim 33 comprising:

a plurality of semiconductor devices located proximate the first surface of the substrate; and

circuit geometry printed in dielectric layers electrically coupling terminals on at least two semiconductor devices.

41. The semiconductor package of claim 33 comprising:

a plurality of semiconductor devices located proximate the first surface of the substrate; and

a plurality of simulated wirebonds electrically coupling terminals on the semiconductor devices to pads on the first surface of the substrate.

42. The semiconductor package of claim 33 comprising:

a plurality of semiconductor devices arranged in a stacked configuration proximate the first surface of the substrate; and

a plurality of simulated wirebonds electrically coupling terminals on the semiconductor devices to pads on the first surface of the substrate.

43. The semiconductor package of claim 33 wherein the conductive traces comprise a stacked configuration with tiered or staggered first contact pads.

44. The semiconductor package of claim 33 wherein the simulated wirebond includes one or more of optical fibers, printed optical material, coaxial conductors, radio-frequency circuits, shielding, or antennae.

45. An electrical assembly comprising:

the semiconductor package of claim 33; and

a circuit member with a plurality of contact pads electrically coupled to the pads on the second surface of the substrate.

46. A method of making a semiconductor package comprising the steps of:

locating a first surface of a semiconductor device proximate a first surface of a substrate;

forming simulated wirebonds including the steps of;

printing at least a first dielectric layer with a plurality of recesses;

locating conductive material in the recesses to form first and second contact pads, and electrical traces electrically coupling the first and second contact pads;

electrically coupling the first contact pads to terminals on a second surface of the semiconductor device and the second contact pads to pads on the first surface of the substrate so the simulated wirebonds extend from the first surface of the substrate to the second surface of the semiconductor device; and

overmolding the semiconductor device and the simulated wirebonds to the first surface of the substrate.

47. The method of claim 46 comprising substantially surrounding the conductive traces with dielectric material.

48. The method of claim 46 comprising extending the conductive traces beyond electrically coupling the first and second contact pads to form circuit geometry.

49. The method of claim 46 comprising printing the dielectric material so the recesses comprise substantially rectangular cross-sectional shapes.

50. The method of claim 46 comprising the steps of:

locating pre-formed conductive trace materials in the recesses; and

plating the recesses to form conductive traces with substantially rectangular cross-sectional shapes.

51. The method of claim 46 wherein printing the conductive traces comprises one or more of printing a conductive material in the recesses and sintering the conductive material or printing a conductive ink in the recesses.

52. The method of claim 46 comprising printing a compliant material in a location between the first dielectric layer and at least one of the contact pads.

53. The method of claim 46 comprising:

printing at least one electrical device on a dielectric layer; and

electrically coupling the electrical device to at least one conductive trace.

54. The method of claim 46 comprising the steps of:

locating a plurality of semiconductor devices proximate the first surface of the substrate; and

electrically coupling the first contact pads to terminals on the semiconductor devices and the second contact pads to pads on the first surface of the substrate.

55. The method of claim 46 comprising the steps of:

locating a plurality of semiconductor devices proximate the first surface of the substrate; and

electrically coupling the first contact pads to terminals on a first semiconductor devices and electrically coupling second contact pads to terminals on a second semiconductor device.

56. A method of making an electrical assembly comprising the steps of:

making the semiconductor package according to the method of claim 46; and

electrically coupling a circuit member with a plurality of the pads on a second surface of the substrate that are electrically coupled to the pads on the first surface of the substrate.