INTEGRATED CIRCUIT PACKAGING SYSTEM WITH PACKAGE-ON-PACKAGE AND METHOD OF MANUFACTURE THEREOF

• US 20120061854A1
• Filed: 09/14/2010
• Published: 03/15/2012
• Est. Priority Date: 09/14/2010
• Status: Active Grant

• Current Assignee: Stats Chippac Pte. Ltd. (JCET Group Co., Ltd.)
• Original Assignee: Stats Chippac BVI limited (JCET Group Co., Ltd.)
• Inventors: Chow, Seng Guan, Goh, Hin Hwa, Huang, Rui, Kuan, Heap Hoe
• Granted Patent: US 8,304,880 B2
• Time in Patent Office: Days
• US Class Current: 257/778
• CPC Class Codes: H01L 21/563 Encapsulation of active face of flip-chip device, e.g. underfilling or underencapsulation of flip-chip, encapsulation preform on chip or mounting substrate
• CPC Class Codes: H01L 2224/16225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/32145 the bodies being stacked
• CPC Class Codes: H01L 2224/32225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/45015 being circular
• CPC Class Codes: H01L 2224/45099 Material
• CPC Class Codes: H01L 2224/48091 Arched
• CPC Class Codes: H01L 2224/48227 connecting the wire to a bond pad of the item
• CPC Class Codes: H01L 2224/73253 Bump and layer connectors
• CPC Class Codes: H01L 2224/73265 Layer and wire connectors
• CPC Class Codes: H01L 2225/0651 Wire or wire-like electrical connections from device to substrate
• CPC Class Codes: H01L 2225/06517 Bump or bump-like direct electrical connections from device to substrate
• CPC Class Codes: H01L 2225/06558 the devices having passive surfaces facing each other, i.e. in a back-to-back arrangement
• CPC Class Codes: H01L 2225/06568 the devices decreasing in size, e.g. pyramidical stack
• CPC Class Codes: H01L 2225/1023 the support being an insulating substrate
• CPC Class Codes: H01L 2225/1058 Bump or bump-like electrical connections, e.g. balls, pillars, posts
• CPC Class Codes: H01L 2225/1094 Thermal management, e.g. cooling
• CPC Class Codes: H01L 24/16 of an individual bump connector
• CPC Class Codes: H01L 24/32 of an individual layer connector
• CPC Class Codes: H01L 24/48 of an individual wire connector
• CPC Class Codes: H01L 24/73 : Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
• CPC Class Codes: H01L 25/0657 : Stacked arrangements of devices
• CPC Class Codes: H01L 25/105 : the devices being of a type provided for in group H01L27/00
• CPC Class Codes: H01L 25/50 : Multistep manufacturing processes of assemblies consisting of devices, each device being of a type provided for in group H01L27/00 or H01L29/00 H01L21/50 takes precedence
• CPC Class Codes: H01L 2924/00 : Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00012 : Relevant to the scope of the group, the symbol of which is combined with the symbol of this group
• CPC Class Codes: H01L 2924/00014 : the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/14 : Integrated circuits
• CPC Class Codes: H01L 2924/15311 : being a ball array, e.g. BGA
• CPC Class Codes: H01L 2924/15331 : being a ball array, e.g. BGA
• CPC Class Codes: H01L 2924/181 : Encapsulation
• CPC Class Codes: H01L 2924/207 : Diameter ranges
• CPC Class Codes: H01L 2924/3511 : Warping

Abstract

A method of manufacture of an integrated circuit packaging system includes: providing a bottom substrate; mounting a bottom integrated circuit over the bottom substrate; mounting a top substrate over a side of the bottom integrated circuit opposite the bottom substrate; connecting a top interconnect between the bottom substrate and the top substrate; and forming an underfill layer between the bottom substrate and the top substrate, the underfill layer encapsulating the top interconnect outside a perimeter of the bottom integrated circuit.

Claims

1. A method of manufacture of an integrated circuit packaging system comprising:

providing a bottom substrate;

mounting a bottom integrated circuit over the bottom substrate;

mounting a top substrate over a side of the bottom integrated circuit opposite the bottom substrate;

connecting a top interconnect between the bottom substrate and the top substrate; and

forming an underfill layer between the bottom substrate and the top substrate, the underfill layer encapsulating the top interconnect outside a perimeter of the bottom integrated circuit.

2. The method as claimed in claim 1 wherein forming the underfill layer includes forming the underfill layer having thermal conduction.

3. The method as claimed in claim 1 wherein forming the underfill layer includes forming the underfill layer having a discontinuous structure adjacent a side of the top substrate.

4. The method as claimed in claim 1 wherein forming the underfill layer includes forming the underfill layer with a material providing fixed spacing between the bottom substrate and the top substrate.

5. The method as claimed in claim 1 further comprising applying a thermal interface layer directly on the bottom integrated circuit and thermally connected to the bottom integrated circuit and the top substrate.

6. A method of manufacture of an integrated circuit packaging system comprising:

providing a bottom substrate;

mounting a bottom integrated circuit over the bottom substrate;

mounting a top substrate over a side of the bottom integrated circuit opposite the bottom substrate, the top substrate having a periphery;

connecting a top interconnect between the bottom substrate and the top substrate; and

forming an underfill layer between the bottom substrate and the top substrate, and between the periphery and the bottom integrated circuit, the underfill layer encapsulating the top interconnect outside a perimeter of the bottom integrated circuit.

7. The method as claimed in claim 6 further comprising forming a bottom encapsulation over the bottom substrate and covering the bottom integrated circuit, the bottom encapsulation adjacent the underfill layer.

8. The method as claimed in claim 6 further comprising mounting a second bottom integrated circuit over the bottom integrated circuit.

9. The method as claimed in claim 6 wherein mounting the bottom integrated circuit includes mounting a flip chip over the bottom substrate.

10. The method as claimed in claim 6 wherein mounting the bottom integrated circuit includes mounting a wirebond device over the bottom substrate.

11. An integrated circuit packaging system comprising:

a bottom substrate;

a bottom integrated circuit over the bottom substrate;

a top substrate over a side of the bottom integrated circuit opposite the bottom substrate;

a top interconnect between the bottom substrate and the top substrate; and

an underfill layer between the bottom substrate and the top substrate, the underfill layer encapsulating the top interconnect, outside a perimeter of the bottom integrated circuit.

12. The system as claimed in claim 11 wherein the underfill layer has thermal conduction.

13. The system as claimed in claim 11 wherein the underfill layer includes a discontinuous structure adjacent a side of the top substrate.

14. The system as claimed in claim 11 wherein the underfill layer is a material providing fixed spacing between the bottom substrate and the top substrate.

15. The system as claimed in claim 11 further comprising a thermal interface layer directly on the bottom integrated circuit and thermally connected to the bottom integrated circuit and the top substrate.

16. The system as claimed in claim 11 wherein:

the top substrate includes a periphery; and

the underfill layer is between the periphery and the bottom integrated circuit.

17. The system as claimed in claim 16 further comprising a bottom encapsulation over the bottom substrate and covering the bottom integrated circuit, the bottom encapsulation adjacent the underfill layer.

18. The system as claimed in claim 16 further comprising a second bottom integrated circuit over the bottom integrated circuit.

19. The system as claimed in claim 16 wherein the bottom integrated circuit is a flip chip over the bottom substrate.

20. The system as claimed in claim 16 wherein the bottom integrated circuit is a wirebond device over the bottom substrate.