SEMICONDUCTOR DEVICE AND SIGNAL TRANSMISSION METHOD

• US 20120062040A1
• Filed: 04/22/2010
• Published: 03/15/2012
• Est. Priority Date: 06/04/2009
• Status: Abandoned Application

• Current Assignee: NEC Corporation
• Original Assignee: NEC Corporation
• Inventors: Kaeriyama, Shunichi
• Application Number:
  US13/321,904
• Publication Number:
  US 20120062040A1
• Time in Patent Office: Days
• US Class Current: 307/104
• CPC Class Codes: H01L 2224/05553 being rectangular
• CPC Class Codes: H01L 2224/45099 Material
• CPC Class Codes: H01L 2224/48091 Arched
• CPC Class Codes: H01L 2224/4813 Connecting within a semiconductor or solid-state body, i.e. fly wire, bridge wire
• CPC Class Codes: H01L 2224/48137 the bodies being arranged next to each other, e.g. on a common substrate
• CPC Class Codes: H01L 2224/49175 Parallel arrangements
• CPC Class Codes: H01L 23/5227 Inductive arrangements or effects of, or between, wiring layers other inductive arrangements H01L23/645
• CPC Class Codes: H01L 27/0688 Integrated circuits having a three-dimensional layout
• CPC Class Codes: H01L 27/08 including only semiconductor components of a single kind
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00014 the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/3025 Electromagnetic shielding

Abstract

A first inductor (310) and a second inductor (320) are formed in a multilayer interconnect layer (400), are wound in a plane parallel to a first substrate (102), and overlap each other. A first circuit (100) connects to either the first inductor (310) or the second inductor (320). At least a portion of the first circuit (100) is located inside the first inductor (310) and the second inductor (320) when seen in a plan view. The first circuit (100) includes a portion having any of a hook-shaped interconnect pattern, a slit-shaped interconnect pattern, and an interconnect pattern that functions as a resistive element or a capacitive element, and the portion is located inside the first inductor (310) and the second inductor (320) when seen in a plan view. In the present embodiment, a hook-shaped interconnect pattern is provided.

Claims

1. A semiconductor device comprising:

a first substrate;

a first circuit formed in the first substrate;

a multilayer interconnect layer formed over the first substrate;

a transmitting inductor formed in the multilayer interconnect layer and wound in a plane parallel to the first substrate; and

a receiving inductor formed in the multilayer interconnect layer and wound in a plane parallel to the first substrate, the receiving inductor overlapping with the transmitting inductor when seen in a plan view,

wherein the first circuit connects to either the transmitting inductor or the receiving inductor,

at least a portion of the first circuit is located inside the transmitting inductor and the receiving inductor when seen in a plan view, and

the first circuit includes a portion having any of a hook-shaped interconnect pattern, a slit-shaped interconnect pattern, and an interconnect pattern that functions as a resistive element or a capacitive element, the portion being located inside the transmitting inductor and the receiving inductor when seen in a plan view.

2. The semiconductor device according to claim 1, wherein the first circuit is a transmitting circuit, and includes a transmitting driver circuit connected to the transmitting inductor, and

the transmitting inductor has both ends connected to the transmitting driver circuit.

3. The semiconductor device according to claim 1, wherein the first circuit is a receiving circuit, and includes any of an amplifier circuit, comparator, and a hysteresis circuit, connected to the receiving inductor.

4. The semiconductor device according to claim 1, wherein the first circuit is a driver circuit,

the driver circuit has an output terminal connected to an external terminal, and

the driver circuit has an output current or a sink current equal to or more than 100 mA.

5. The semiconductor device according to claim 1, wherein the first circuit is a driver circuit,

the driver circuit has an output terminal connected to an external terminal, and

the driver circuit has an on-resistance equal to or less than 100 Ω

.

6. The semiconductor device according to claim 1, wherein the first circuit is a filter circuit.

7. The semiconductor device according to claim 6, wherein the filter circuit includes a resistive element made of polysilicon or a capacitive element.

8. The semiconductor device according to claim 6, wherein the filter circuit includes a resistive element or a capacitive element, having a well layer or a diffusion layer.

9. The semiconductor device according to claim 1, wherein the first circuit is an inverter circuit.

10. The semiconductor device according to claim 1, further comprising an electromagnetic shielding interconnect pattern formed in an interconnect layer, the interconnect layer being located between the transmitting inductor/the receiving inductor and the first substrate, the electromagnetic shielding interconnect pattern overlapping with the first circuit when seen in a plan view, and being grounded.

11. The semiconductor device according to claim 10, wherein the centers of the transmitting inductor and the receiving inductor overlap each other, and

the electromagnetic shielding interconnect pattern is formed so as to radially extend from the vicinity of the center of the transmitting inductor and the receiving inductor.

12. The semiconductor device according to claim 1, wherein the first circuit includes a loop-shaped interconnect pattern, and

the loop-shaped interconnect pattern has a diameter equal to or less than one-tenth of that of the transmitting inductor or of the receiving inductor.

13. The semiconductor device according to claim 1, wherein the first circuit is composed of the first substrate and only an interconnect layer lowermost in the multilayer interconnect layer, the multilayer interconnect layer being formed over the first substrate.

14. The semiconductor device according to claim 13, wherein either the transmitting inductor or the receiving inductor connects to the first circuit, and is formed in an interconnect layer of the multilayer interconnect layer formed over the first substrate, and the interconnect layer is higher by one layer than a layer lowermost in the multilayer interconnect layer.

15. A signal transmission method, in which a semiconductor device includes a first substrate;

a first circuit formed in the first substrate;

a multilayer interconnect layer formed over the first substrate;

a transmitting inductor formed in the multilayer interconnect layer and wound in a plane parallel to the first substrate; and

a receiving inductor formed in the multilayer interconnect layer and wound in a plane parallel to the first substrate, the receiving inductor overlapping with the transmitting inductor when seen in a plan view,

the method comprising;

connecting the first circuit to either the transmitting inductor or the receiving inductor;

causing at least a portion of the first circuit to be located inside the transmitting inductor and the receiving inductor in a plan view;

providing a portion of the first circuit with any of a hook-shaped interconnect pattern, a slit-shaped interconnect pattern, and an interconnect pattern that functions as a resistive element or a capacitive element, the portion being located inside the transmitting inductor and the receiving inductor when seen in a plan view; and

inputting a transmitting signal to the transmitting inductor and inductively coupling the transmitting inductor and the receiving inductor so as to transmit the transmitting signal to the receiving inductor.