METHOD OF MANUFACTURING AN INTEGRATED CIRCUIT AND PHOTOSENSOR CELL WITH SELECTIVELY SILICIDED GATES
First Claim
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1. A CMOS active pixel image sensor, comprising:
- an array of pixels, at least one pixel of the array bounded at least partially by an isolation region and comprising;
a p-n junction photodiode to produce photo-generated charge;
a floating diffusion node;
a transfer transistor, including a polysilicon transfer gate, adjacent to the photodiode and to the node, the transfer configured to transfer the charge from the photodiode to the node;
a reset transistor, including a polysilicon reset gate, coupled to the node and to an n+ diffusion region configured to be coupled to a voltage source, the reset transistor configured to transfer voltage from the voltage source to the node;
a source follower transistor, including a polysilicon source follower gate, coupled to the node; and
silicide located on a surface of each one of the polysilicon transfer gate, the polysilicon reset gate, and the polysilicon source of the photodiode and a surface of the node;
a readout circuit configured to provide correlated sampling of the pixel;
an analog-to-digital converter; and
image processing circuitry.
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Abstract
The invention also relates to an apparatus and method for selectively providing a silicide coating over the transistor gates of a CMOS imager to improve the speed of the transistor gates. The method further includes an apparatus and method for forming a self aligned photo shield over the CMOS imager.
11 Citations
43 Claims
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1. A CMOS active pixel image sensor, comprising:
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an array of pixels, at least one pixel of the array bounded at least partially by an isolation region and comprising; a p-n junction photodiode to produce photo-generated charge; a floating diffusion node; a transfer transistor, including a polysilicon transfer gate, adjacent to the photodiode and to the node, the transfer configured to transfer the charge from the photodiode to the node; a reset transistor, including a polysilicon reset gate, coupled to the node and to an n+ diffusion region configured to be coupled to a voltage source, the reset transistor configured to transfer voltage from the voltage source to the node; a source follower transistor, including a polysilicon source follower gate, coupled to the node; and silicide located on a surface of each one of the polysilicon transfer gate, the polysilicon reset gate, and the polysilicon source of the photodiode and a surface of the node; a readout circuit configured to provide correlated sampling of the pixel; an analog-to-digital converter; and image processing circuitry. - View Dependent Claims (2)
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3. A CMOS active pixel imager, comprising:
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an array of pixels, at least one pixel of the array comprising; a shallow trench isolation region; a photodiode having a surface region free of silicide; a transfer transistor to transfer charge from the photodiode to a node, the transfer transistor having a silicided gate and having a surface of a source/drain region substantially free of silicide; a reset transistor coupled between the node and the voltage source, the reset transistor having a silicided gate and having a surface of a source/drain region substantially free of silicide; and a source follower transistor having a silicided gate coupled to the node and having a surface of a source/drain region substantially free of silicide; a readout circuit configured to provide correlated sampling of each pixel; an analog-to-digital converter; and image processing circuitry. - View Dependent Claims (4)
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5. A camera system, comprising:
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a bus; a processor; random access memory coupled to the processor via the bus; a CMOS active pixel imager coupled to the processor via the bus, the imager comprising a plurality of pixels each containing silicided transistor gates, transistor source/drain regions free from silicide, a photodiode, and shallow trench isolation, the imager configured to perform correlated sampling of each pixel, analog-to-digital conversion of the output of each pixel, and image processing.
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6. A CMOS imager, comprising:
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an array of pixels, at least one pixel comprising; a photo-collection region to accumulate photo-generated charge, wherein silicide is substantially absent from a surface of the photosensor; a transfer transistor to transfer the charge from the photo-collection region to a storage node, wherein the transfer transistor includes a polysilicon transfer gate comprising silicide and the storage node is substantially free of silicide. - View Dependent Claims (7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17)
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18. A CMOS imager, comprising:
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a pixel array comprising a plurality of photosensors to accumulate photogenerated charges and a plurality of reset transistors each having a reset gate, each reset transistor capable of resetting a corresponding one of the photosensors, wherein the reset gates include a conductive layer comprising a refractory metal, and wherein the regions above the photosensors and above the sources and drains of the reset transistors are free of the conductive layer; timing and control circuitry to read out pixels of the array; and an analog-to-digital converter coupled to receive signals from pixels of the array. - View Dependent Claims (19, 20, 21, 22, 23, 24, 25, 26)
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27. An apparatus, comprising:
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a pixel array, each pixel of the array comprising at least one silicided transistor gate, at least one transistor source/drain that is not silicided, and at least one photosensor that is not silicided to prevent light blockage; a readout circuit configured to provide correlated sampling of each pixel of the array; and an analog-to-digital converter coupled to receive signals from pixels of the array. - View Dependent Claims (28, 29, 30, 31, 32, 33, 34, 35)
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36. A camera system, comprising:
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a processor; random access memory coupled to the processor; a non-volatile memory subsystem coupled to the processor and configured to enable use of removable storage media; and a CMOS imager, coupled to the processor, comprising a pixel array having silicided gates of transistors, unsilicided source/drain regions of the transistors, and an analog-to-digital converter. - View Dependent Claims (37, 38, 39, 40, 41, 42, 43)
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Specification