Reconfigurable Multi-level Sensing Scheme for Semiconductor Memories
First Claim
1. A method for sensing at least one parameter indicative of a logical state of a multi-level memory cell, the method comprising the steps of:
- measuring the at least one parameter of the multi-level memory cell;
comparing the measured at least one parameter of the multi-level memory cell with a prescribed reference signal, the reference signal having a value which varies as a function of time; and
storing a time value corresponding to a point in time at which the reference signal is substantially equal to the measured at least one parameter of the multi-level memory cell, the stored time value being indicative of a sensed logical state of the multi-level memory cell.
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Abstract
A method for sensing at least one parameter indicative of a logical state of a multi-level memory cell includes the steps of: measuring the parameter of the multi-level memory cell; comparing the measured parameter of the multi-level memory cell with a prescribed reference signal, the reference signal having a value which varies as a function of time; and storing a time value corresponding to a point in time at which the reference signal is substantially equal to the measured parameter of the multi-level memory cell, the stored time value being indicative of a sensed logical state of the multi-level memory cell.
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Citations
20 Claims
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1. A method for sensing at least one parameter indicative of a logical state of a multi-level memory cell, the method comprising the steps of:
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measuring the at least one parameter of the multi-level memory cell; comparing the measured at least one parameter of the multi-level memory cell with a prescribed reference signal, the reference signal having a value which varies as a function of time; and storing a time value corresponding to a point in time at which the reference signal is substantially equal to the measured at least one parameter of the multi-level memory cell, the stored time value being indicative of a sensed logical state of the multi-level memory cell. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8)
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9. A sense circuit for sensing at least one parameter indicative of a state of a multi-level memory cell, the sense circuit comprising:
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a reference generator operative to generate a reference signal having a value which dynamically varies as a function of time; a monitor circuit operative to measure the at least one parameter of the multi-level memory cell and to generate a sensed parameter signal indicative of a state of the multi-level memory cell; a comparator operative to receive the reference signal and the sensed parameter signal and to generate an output signal as a function of a difference between the reference signal and the sensed parameter signal; and memory operative as a function of the output signal generated by the comparator to store a time value corresponding to a point in time at which the reference signal is substantially equal to the sensed parameter signal, the stored time value being indicative of a sensed logical state of the multi-level memory cell. - View Dependent Claims (10, 11, 12, 13, 14, 15, 16, 17, 18, 19)
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20. A memory circuit, comprising:
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a memory array including a plurality of multi-level memory cells and at least one word line and a plurality of bit lines coupled with the memory cells for selectively accessing the cells; and at least one sense circuit connected with a corresponding one of the bit lines and being operative to sense at least one parameter indicative of a state of a multi-level memory cell, the at least one sense circuit comprising; a reference signal generator operative to generate a reference signal having a value which dynamically varies as a function of time; a monitor circuit operative to measure the at least one parameter of the multi-level memory cell and to generate a sensed parameter signal indicative of a state of the multi-level memory cell; a comparator operative to receive the reference signal and the sensed parameter signal and to generate an output signal as a function of a difference between the reference signal and the sensed parameter signal; and a storage element operative, as a function of the output signal generated by the comparator, to store a time value corresponding to a point in time at which the reference signal is substantially equal to the sensed parameter signal, the stored time value being indicative of a sensed logical state of the multi-level memory cell.
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Specification