SEMICONDUCTOR DEVICE

• US 20120063204A1
• Filed: 09/02/2011
• Published: 03/15/2012
• Est. Priority Date: 09/10/2010
• Status: Active Grant

• Current Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Original Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Inventors: Kamata, Koichiro
• Granted Patent: US 8,358,530 B2
• Time in Patent Office: Days
• US Class Current: 365/149
• CPC Class Codes: G11C 16/0466 comprising cells with charge storage in an insulating layer, e.g. metal-nitride-oxide-silicon [MNOS], silicon-oxide-nitride-oxide-silicon [SONOS] G11C16/0483, G11C16/0491 take precedence
• CPC Class Codes: H01L 27/1207 combined with devices in contact with the semiconductor body, i.e. bulk/SOI hybrid circuits
• CPC Class Codes: H01L 27/1225 with semiconductor materials not belonging to the group IV of the periodic table, e.g. InGaZnO
• CPC Class Codes: H10B 41/00 Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates

Abstract

One object is to provide a novel semiconductor device which can hold stored data even when not powered and which has an unlimited number of writing operations. Another object is to reduce a circuit size and to improve reliability of writing and reading of data. When a memory cell using a transistor including an oxide semiconductor layer is subjected to the verification operation and reading of data, a dual-gate transistor showing different threshold voltages is used as a resistor; thus, stable verification operation and reading operation can be performed by only a reference potential circuit.

Claims

1. A semiconductor device comprising:

a memory cell including a first transistor, a second transistor, and a capacitor, wherein a first gate terminal of the first transistor is electrically connected to the capacitor, a first source terminal of the first transistor is electrically connected to a bit line, and the first transistor includes a semiconductor substrate, wherein a second gate terminal of the second transistor is electrically connected to a word line for an oxide semiconductor, a second source terminal of the second transistor is electrically connected to a bit line for an oxide semiconductor, a second drain terminal of the second transistor is electrically connected to the first gate terminal of the first transistor, and the second transistor includes an oxide semiconductor layer;

a resistor comprising a dual-gate transistor including a third source terminal, a third drain terminal, a third gate terminal, and a fourth gate terminal, wherein the third source terminal and the third gate terminal are electrically connected to a terminal to which power supply voltage is input, and the third drain terminal is electrically connected to the bit line;

a reference potential circuit configured to output a reference potential;

a potential comparison circuit electrically connected to the reference potential circuit and the bit line, the potential comparison circuit configured to compare the reference potential output by the reference potential circuit with a potential of the bit line; and

a control circuit electrically connected to the potential comparison circuit, wherein an output potential of the potential comparison circuit is supplied to a power supply control circuit portion and a state change circuit portion,

wherein the state change circuit portion is electrically connected to an input portion of the power supply control circuit portion and the fourth gate terminal of the resistor, and is configured to supply a potential to the fourth gate terminal, and

wherein the power supply control circuit portion is electrically connected to the bit line for the oxide semiconductor, and is configured to supply a potential to the bit line for the oxide semiconductor.

2. The semiconductor device according to claim 1, wherein the reference potential circuit is a plurality of reference potential circuits configured to output respective potentials.

3. The semiconductor device according to claim 1, wherein the semiconductor substrate is a single crystal semiconductor substrate.

4. The semiconductor device according to claim 1, wherein the semiconductor substrate includes silicon.

5. The semiconductor device according to claim 1, wherein the oxide semiconductor layer is an oxide semiconductor material including In, Ga, and Zn.