Most compact flotox-based combo NVM design without sacrificing EEPROM endurance cycles for 1-die data and code storage

• US 20120063223A1
• Filed: 09/09/2011
• Published: 03/15/2012
• Est. Priority Date: 09/09/2010
• Status: Abandoned Application

• Current Assignee: Aplus Flash Technology, Inc.
• Original Assignee: Aplus Flash Technology, Inc.
• Inventors: Lee, Peter Wung, Hsu, Fu-Chang
• Application Number:
  US13/199,785
• Publication Number:
  US 20120063223A1
• Time in Patent Office: Days
• US Class Current: 365/185.02
• CPC Class Codes: G11C 11/005 comprising combined but independently operative RAM-ROM, RAM-PROM, RAM-EPROM cells
• CPC Class Codes: G11C 16/0433 comprising cells containing a single floating gate transistor and one or more separate select transistors
• CPC Class Codes: G11C 16/12 Programming voltage switching circuits
• CPC Class Codes: G11C 16/3436 Arrangements for verifying correct programming or erasure

Abstract

Disclosed is a low-cost hybrid storage solution that allows Code like sector-alterable NOR and Data like block-alterable NAND and byte-alterable EEPROM being integrated on a same die. The disclosed combo NVM design of the present invention is a truly Data-oriented NVM design that allows 2T-EEPROM to integrate both 0.5T-NAND and 1T-NOR without sacrificing any EEPROM'"'"'s byte-write performance in the same die. The invention provides several new embodiment sets of preferable bias conditions of Program, Program-Inhibit, Erase and Erase-Inhibit for operating bit-write, byte-write, sector-write and page-write for several preferable Flotox-based EEPROM, NOR and NAND or combo NVM arrays that include types of shared SL, 8-pair BLs and SLS, with or without GBL, normally Erased Vt and Programmed Vt, or the reversed Erased-Vt or Programmed-Vt, etc. Further disclosed is a flexible X-decoder design to allow the flexible selection of pages to be erased to save erase time. Also disclosed is using on-chip negative voltage for FT'"'"'s gate along with the less positive HV applied to FTs'"'"' channel region for same write performance but with the benefits of channel length reduction in cell and less BVDS electric requirement in peripheral devices for more scalable manufacturing process.

Claims

1. A FLOTOX (FT) based 1 T EEPROM NOR cell circuit, comprising:

not more than one high voltage (HV) floating gate FT transistor without requiring a bit-line select transistor, having a gate, a drain and a source, wherein a drain of the FT transistor is connected to a bit line, a source is connected to a source line and a gate is connected to word line;

wherein a bias condition reduces bit line program disturb.

2. The 1 T EEPROM NOR cell of claim 1 formed on top of a P-substrate, one gate of said transistor;

a floating gate underneath said gate, and a tunnelling oxide layer underneath of each of floating gates;

a first Boron-Nitride (BN+) region in the P-substrate connected to the source line; and

a second Boron-Nitride (BN+) region in the P-substrate connected to the bit line.

3. A negative gate program to bias for operating a 2T EEPROM cell performed in unit of byte comprising a bit line select (BL-ST) transistor and a floating gate Fowler-Nordheim (FN) transistors, wherein the source of the FN is denoted as source line (SL), the drain of the FN-transistor is denoted as bit line, the gate of the BL-ST is denoted as word-line (WL), and the gate of the FN-transistor is denoted as control gate (CG) with P-substrate tied to ground level:

biasing for Erase operation is performed by applying VPP1 voltage to WL and to CG, floating voltage to SL and 0V to BL;

biasing for Erase inhibit operation is performed by applying VPP1 voltage to WL and to CG, floating voltage to SL and VPP2 voltage to BL;

biasing for Program operation is performed by applying VPP1 voltage to WL, VNN1 voltage to CG, VPP5 voltage to BL, and floating voltage to SL;

biasing for Program inhibit operation is performed by applying VPP1 voltage to WL, VNN1 voltage to CG, and floating voltage to BL and SL; and

biasing for Read operation is performed by applying Vdd voltage to WL, Vread voltage to CG, a voltage smaller than 1.0 V to BL, and 0V to SL;

wherein VPP1=16V, VPP2=8-16V, Vpp5=8-10 V, and Vread=1.8-3.0V.

4. A source line erase-inhibit program to bias for operating a 2T EEPROM cell performed in unit of byte comprising a bit line select (BL-ST) transistor and a floating gate Fowler-Nordheim (FN) transistors, wherein the source of the FN is denoted as source line (SL), the drain of the FN-transistor is denoted as bit line, the gate of the BL-ST is denoted as word-line (WL), and the gate of the FN-transistor is denoted as control gate (CG) with P-substrate tied to ground level:

biasing for Erase operation is performed by applying VPP1 voltage to WL and to CG, floating voltage to BL and 0V to SL;

biasing for Erase inhibit operation is performed by applying VPP1 voltage to WL and to CG, floating voltage to BL and VPP2 voltage to SL;

biasing for Program operation is performed by applying VPP1 voltage to WL, 0V to CG, VPP1 voltage to BL, and floating voltage to SL;

biasing for Program inhibit operation is performed by applying VPP1 voltage to WL, 0V to CG, and floating voltage to BL and SL; and

biasing for Read operation is performed by applying Vdd voltage to WL, Vread voltage to CG, a voltage smaller than 1.0 V to BL, and 0V to SL;

wherein VPP1=16V, VPP2=8-16V, and Vread=1.8-3.0 V.

5. A method to bias for operating a 2T EEPROM cell, wherein preferable program and erase operations are reversed, performed in unit of byte comprising a bit line select (BL-ST) transistor and a floating gate Fowler-Nordheim (FN) transistors, wherein the source of the FN is denoted as source line (SL), the drain of the FN-transistor is denoted as bit line, the gate of the BL-ST is denoted as word-line (WL), and the gate of the FN-transistor is denoted as control gate (CG) with P-substrate tied to ground level:

biasing for Erase operation is performed by applying VPP1 voltage to WL and to BL, floating voltage to SL, and 0V to CG;

biasing for Erase inhibit operation is performed by applying VPP1 voltage to WL, 0V to CG, floating voltage to SL and to BL;

biasing for Program operation is performed by applying VPP1 voltage to WL and to CG, 0V to BL, and floating voltage to SL;

biasing for Program inhibit operation is performed by applying VPP1 voltage to WL and to CG, and VPP2 voltage to BL, and floating voltage to SL; and

biasing for Read operation is performed by applying Vdd voltage to WL, Vread voltage to CG, a voltage smaller than 1.0 V to BL, and 0V to SL;

wherein VPP1=16V, VPP2=8-16V, and Vread=1.8-3.0 V.

6. A bit-erase bias method for operating a 2T EEPROM cell performed in unit of bit comprising a bit line select (BL-ST) transistor and a floating gate Fowler-Nordheim (FN) transistors, wherein the source of the FN is denoted as source line (SL), the drain of the FN-transistor is denoted as bit line, the gate of the BL-ST is denoted as word-line (WL), and the gate of the FN-transistor is denoted as control gate (CG) with P-substrate tied to ground level:

biasing for Erase operation is performed by applying VPP1 voltage to WL and to CG, floating voltage to SL and 0V to BL;

biasing for Erase inhibit operation is performed by applying VPP1 voltage to WL and to CG, floating voltage to SL and VPP2 voltage to BL;

biasing for Program operation is performed by applying VPP1 voltage to WL and to BL, 0V to CG, and floating voltage to SL;

biasing for Program inhibit operation is performed by applying VPP1 voltage to WL, 0V to CG, and floating voltage to SL and to BL; and

biasing for Read operation is performed by applying Vdd voltage to WL, Vread voltage to CG, a voltage smaller than 1.0 V to BL, and 0V to SL;

wherein VPP1=16V, VPP2=8-16V, and Vread=1.8-3.0 V.

7. A two-transistor (2T) FLOTOX-based EEPROM cell array comprising:

a matrix of a plurality of 2T FLOTOX EEPROM cells arranged in word-line circuits, which are arranged in rows and columns, each word line circuit comprising N+1 bytes, wherein each 2T-cell comprises;

a select transistor (ST); and

a floating gate Fowler-Nordheim (FN) transistor having a drain merged with a source of the associated select transistor;

a plurality of bit lines, each bit line associated with one column of the 2T FLOTOX EEPROM cells such that each bit line is connected to the drains of the 2T FLOTOX EEPROM cells of the associated column;

a plurality of vertical common source lines, each common source line is shared by a multitude of pairs of two vertical bytes and is connected to all source nodes of the multitude of the pairs of two vertical bytes represented by the floating gate transistors;

a plurality of word lines, each word line associated with one row of the 2T FLOTOX EEPROM cells and connected to the gates of the select transistors of the associated row of two-transistor FLOTOX EEPROM cells and perpendicular to the bit lines and the source lines;

a plurality of common signal lines, each common signal line associated with one row of the 2T FLOTOX EEPROM cells and connected to the gates of the floating gate transistors of the associated row of two-transistor FLOTOX EEPROM cells and perpendicular to the bit lines and the source lines;

wherein no byte-select transistors and no global bit lines are needed and a whole page of the EEPROM array comprises multiple bytes cascaded in x-direction.

8. The two-transistor (2T) FLOTOX-based EEPROM cell array of claim 7, wherein a method to bias for Erase and Erase-Inhibit conditions in unit of page comprising the select (ST) transistors and the floating gate (FN) transistors, wherein the word lines are denoted by WL, the control gates by CG, the bit lines of a byte having n bytes are denoted as BL[0:

n] and the common source lines for vertical bytes are denoted as source line (SL);

biasing for Erase and Erase-inhibit condition for selected page and selected bytes is performed by applying VPP1 voltage to WL and to CG, floating voltage to SL, and 0V to BL;

biasing for Erase and Erase inhibit operation for selected pages and unselected bytes is performed by applying VPP1 voltage to WL and to CG, floating voltage to SL and VPP2 voltage to BL;

biasing for Erase and Erase-inhibit condition for unselected pages and selected bytes is performed by applying VPP3 voltage to WL, floating voltage to SL, and 0V to BL and CG; and

biasing for Erase and Erase-inhibit condition for unselected pages and unselected bytes is performed by applying VPP3 voltage to WL, floating voltage to SL, VPP2 voltage to BL, and 0V to CG;

wherein all the erase-Inhibit voltage are coupled from selected BLs to the channels of selected cells and keep their corresponding SLs floating to prevent the selected cells'"'"' channels from punch-through and VPP1 is about 16V, VPP2 is about 8-16 V, and VPP3 is about 0-8V.

9. The two-transistor (2T) FLOTOX-based EEPROM cell array of claim 7, wherein a method to bias for Program and Program-Inhibit conditions in unit of page comprising the select (ST) transistors and the floating gate (FN) transistors, wherein the word lines are denoted by WL, the control gates by CG, the bit lines of a byte having n bytes are denoted as BL[0:

n] and the common source lines for vertical bytes are denoted as source line (SL);

biasing for Program and Program-inhibit condition for selected page and selected bytes is performed by applying VPP1 voltage to WL and to BL, floating voltage to SL, and 0V to CG;

biasing for Program and Program-Inhibit operation for selected page and unselected bytes is performed by applying VPP1 voltage to WL, floating voltage to SL and to BL, and 0V to CG;

biasing for Program and Program-Inhibit condition for unselected pages and selected bytes is performed by applying VPP3 voltage to WL, floating voltage to SL, 0V to CG; and

VPP1 voltage to BL; and

biasing for Program and Program-Inhibit condition for unselected pages and unselected bytes is performed by applying VPP3 voltage to WL, floating voltage to SL and BL, and 0V to CG;

wherein all the Program-Inhibit voltages are coupled from selected BLs to the channels of selected cells and keep their corresponding SLs floating to prevent the selected cells'"'"' channels from punch-through and wherein VPP1 is about 15-18V, and VPP3 is about 0-8V.

10. The two-transistor FLOTOX-EEPROM cell array of claim 7, wherein each page length is increased in x-direction, wherein each page comprises a plurality of sectors, each sector in a page comprising only one common global bit line, one byte select transistor, and all (k+1) bytes of a sector are sharing one vertical source line per byte, wherein the total number of bytes of a page is increased to (K+1)×

(N+1).

11. The two-transistor (2T) FLOTOX-based EEPROM cell array of claim 10, wherein a method to bias for Erase and Erase-Inhibit conditions in unit of page comprising the select (ST) transistors and the floating gate (FN) transistors, wherein the word lines are denoted by WL, the global bit lines are denoted as GBL, the bit lines of a byte having n bytes are denoted as BL[0:

n] and the common source lines for vertical bytes are denoted as source line (SL);

biasing for Erase and Erase-inhibit condition for selected page and selected bytes in a selected sector is performed by applying VPP1 voltage to WL and to GBL, floating voltage to SL, and 0V to BL;

biasing for Erase and Erase inhibit operation for selected pages and unselected bytes in a selected sector is performed by applying VPP1 voltage to WL and GBL, floating voltage to SL, and VPP2 voltage to BL;

biasing for Erase and Erase-inhibit condition for unselected pages and selected bytes in a selected sector is performed by applying VPP3 voltage to WL, floating voltage to SL, 0V to BL, and VPP1 voltage to GBL;

biasing for Erase and Erase-inhibit condition for unselected pages and unselected bytes in a selected sector is performed by applying VPP3 voltage to WL, floating voltage to SL, and VPP2 voltage to BL, and VPP1 voltage to GBL;

biasing for Erase and Erase-inhibit condition for selected page and unselected bytes in an unselected sector is performed by applying VPP1 voltage to WL, 0V to GBL and to BL, and floating voltage to SL; and

biasing for Erase and Erase-inhibit condition for unselected pages and unselected bytes in an unselected sector is performed by applying VPP3 voltage to WL, floating voltage to SL, and 0V to BL and to GBL;

wherein all the erase-Inhibit voltages are coupled from selected BLs to the channels of selected cells and keep their corresponding SLs floating to prevent the selected cells'"'"' channels from punch-through and wherein VPP1 is about 15-18V, VPP2 is about 6-18 V, and VPP3 is about 0-8V.

12. The two-transistor (2T) FLOTOX-based EEPROM cell array of claim 10, wherein a method to bias for Program and Program-Inhibit conditions in unit of page comprising the select (ST) transistors and the floating gate (FN) transistors, wherein the word lines are denoted by WL, the global bitlines are denoted as GBL, the bit lines of a byte having n bytes are denoted as BL[0:

n] and the common source lines for vertical bytes are denoted as source line (SL);

biasing for Program and Program Inhibit condition for selected page and selected bytes in a selected sector is performed by applying VPP1 voltage to WL and to BL, floating voltage to SL, and 0V to GBL;

biasing for Program and Program Inhibit condition for selected page and unselected bytes in a selected sector is performed by applying VPP1 voltage to WL, 0V to GBL, and floating voltage to SL and BL;

biasing for Program and Program Inhibit condition for unselected pages and selected bytes in a selected sector is performed by applying 0V to WL and GBL, floating voltage to SL, and VPP1 voltage to BL;

biasing for Program and Program Inhibit condition for unselected pages and unselected bytes in a selected sector is performed by applying 0V to WL and to GBL, and floating voltage to SL and to BL;

biasing for Program and Program Inhibit condition for selected pages and unselected bytes in an unselected sector is performed by applying VPP1 voltage to WL, floating voltage to SL and to BL, and 0V to GBL;

biasing for Program and Program Inhibit condition for unselected pages and unselected bytes in an unselected sector is performed by applying 0V to WL and to GBL, and floating voltage to SL and to BL;

wherein all the Program-Inhibit voltages are coupled from selected BLs to the channels of selected cells and keep their corresponding SLs floating to prevent the selected cells'"'"' channels from punch-through and wherein VPP1 is about 15-18V, and VPP3 is about 0-8V.

13. The two-transistor (2T) FLOTOX-based EEPROM cell array of claim 10, wherein instead of shared source lines eight vertical source lines are connected to eight sources of a single byte of eight 2T EEPROM cells.

14. The two-transistor (2T) FLOTOX-based EEPROM cell array of claim 13, wherein a method to bias for Erase and Erase-Inhibit conditions in unit of page comprising the select (ST) transistors and the floating gate (FN) transistors, wherein the word lines are denoted by WL, the global bit lines are denoted as GBL, the bit lines of a byte having n bytes are denoted as BL[0:

n] and the common source lines for vertical bytes are denoted as source line (SL);

biasing for Erase and Erase-inhibit condition for selected page and selected bytes in a selected sector is performed by applying VPP1 voltage to WL and to GBL, floating voltage to SL, and 0V to BL;

biasing for Erase and Erase inhibit operation for selected pages and unselected bytes in a selected sector is performed by applying VPP1 voltage to WL and GBL, floating voltage to SL, and VPP2 voltage to BL;

biasing for Erase and Erase-inhibit condition for unselected pages and selected bytes in a selected sector is performed by applying VPP3 voltage to WL, floating voltage to SL, 0V to BL, and VPP1 voltage to GBL;

biasing for Erase and Erase-inhibit condition for unselected pages and unselected bytes in a selected sector is performed by applying VPP3 voltage to WL, floating voltage to SL, and VPP2 voltage to BL, and VPP1 voltage to GBL;

biasing for Erase and Erase-inhibit condition for selected page and unselected bytes in an unselected sector is performed by applying VPP1 voltage to WL, 0V to GBL and to BL, and floating voltage to SL; and

biasing for Erase and Erase-inhibit condition for unselected pages and unselected bytes in an unselected sector is performed by applying VPP3 voltage to WL, floating voltage to SL, and 0V to BL and to GBL;

wherein all the erase-Inhibit voltages are coupled from selected BLs to the channels of selected cells and keep their corresponding SLs floating to prevent the selected cells'"'"' channels from punch-through VPP1 is about 15-18V, VPP2 is about 6-18 V, and VPP3 is about 0-8V.

15. The two-transistor (2T) FLOTOX-based EEPROM cell array of claim 13, wherein a method to bias for Program and Program-Inhibit conditions in unit of page comprising the select (ST) transistors and the floating gate (FN) transistors, wherein the word lines are denoted by WL, the global bitlines are denoted as GBL, the bit lines of a byte having n bytes are denoted as BL[0:

n] and the common source lines for vertical bytes are denoted as source line (SL);

biasing for Program and Program Inhibit condition for selected page and selected bytes in a selected sector is performed by applying VPP1 voltage to WL and to BL, floating voltage to SL, and 0V to GBL;

biasing for Program and Program Inhibit condition for selected page and unselected bytes in a selected sector is performed by applying VPP1 voltage to WL, 0V to GBL, and floating voltage to SL and BL;

biasing for Program and Program Inhibit condition for unselected pages and selected bytes in a selected sector is performed by applying VPP3 voltage to WL, floating voltage to SL, 0V to GBL, and VPP1 voltage to BL;

biasing for Program and Program Inhibit condition for unselected pages and unselected bytes in a selected sector is performed by applying VPP3 voltage to WL, 0V to GBL, and floating voltage to SL and to BL;

biasing for Program and Program Inhibit condition for selected pages and unselected bytes in an unselected sector is performed by applying VPP1 voltage to WL, floating voltage to SL and to BL, and 0V to GBL;

biasing for Program and Program Inhibit condition for unselected pages and unselected bytes in an unselected sector is performed by applying VPP3 voltage to WL, 0V to GBL, and floating voltage to SL and to BL;

wherein all the Program-Inhibit voltages are coupled from selected BLs to the channels of selected cells and keep their corresponding SLs floating to prevent the selected cells'"'"' channels from punch-through and wherein VPP1 is about 15-18V and VPP3 is about 0-8V.

16. The two-transistor FLOTOX-EEPROM cell array of claim 7, wherein each page has (N+1) independent bytes with a layout being cascaded in x-direction in one large page wherein each page length is increased in x-direction, wherein all vertical bytes are sharing one common vertical source line with totally (N+1) independent source lines connected to the common source nodes of all vertical bytes running in Y-direction.

17. The two-transistor (2T) FLOTOX-based EEPROM cell array of claim 16, wherein a method to bias for Erase and Erase-Inhibit conditions in unit of page comprising the select (ST) transistors and the floating gate (FN) transistors, wherein the word lines are denoted by WL, the control gates by CG, the bit lines of a byte having n bytes are denoted as BL[0:

n] and the common source lines for vertical bytes are denoted as source line (SL);

biasing for Erase and Erase-inhibit condition for selected page and selected bytes is performed by applying VPP1 voltage to WL and to CG, floating voltage to SL, and 0V to BL;

biasing for Erase and Erase inhibit operation for selected pages and unselected bytes is performed by applying VPP1 voltage to WL and to CG, floating voltage to SL and VPP2 voltage to BL;

biasing for Erase and Erase-inhibit condition for unselected pages and selected bytes is performed by applying VPP3 voltage to WL, floating voltage to SL, and 0V to BL and to CG; and

biasing for Erase and Erase-inhibit condition for unselected pages and unselected bytes is performed by applying VPP3 voltage to WL, floating voltage to SL, VPP2 voltage to BL, and 0V to CG;

wherein all the Erase-Inhibit voltage are coupled from selected BLs to the channels of selected cells and keep their corresponding SLs floating to prevent the selected cells'"'"' channels from punch-through and wherein VPP1 is about 16V, VPP2 is about 6-18 V, and VPP3 is about 0-8V.

18. The two-transistor (2T) FLOTOX-based EEPROM cell array of claim 16, wherein a method to bias for Program and Program-Inhibit conditions in unit of page comprising the select (ST) transistors and the floating gate (FN) transistors, wherein the word lines are denoted by WL, the control gates by CG, the bit lines of a byte having n bytes are denoted as BL[0:

n] and the common source lines for vertical bytes are denoted as source line (SL);

biasing for Program and Program-inhibit condition for selected page and selected bytes is performed by applying VPP1 voltage to WL, floating voltage to SL, VPP5 voltage to BL, and VNN1 voltage to CG;

biasing for Program and Program-Inhibit operation for selected page and unselected bytes is performed by applying VPP1 voltage to WL, floating voltage to SL and to BL, and VNN1 voltage to CG;

biasing for Program and Program-Inhibit condition for unselected pages and selected bytes is performed by applying VPP3 voltage to WL, floating voltage to SL, 0V to CG; and

VPP5 voltage to BL; and

biasing for Program and Program-Inhibit condition for unselected pages and unselected bytes is performed by applying VPP3 voltage to WL, floating voltage to SL and BL, and 0V to CG;

wherein all the Program-Inhibit voltages are coupled from selected BLs to the channels of selected cells and keep their corresponding SLs floating to prevent the selected cells'"'"' channels from punch-through and VPP1 is about 16V, VNN1=−

1-−

8V, VPP5=8V-10V, and VPP3 is about 0-8V.

19. The two-transistor (2T) FLOTOX-based EEPROM cell array of claim 7, wherein a method to bias for Erase and Erase-Inhibit conditions are set to be different for the selected bytes and the unselected bytes on the selected and unselected pages so that the least program and erase disturbance can be achieved, comprising the select (ST) transistors and the floating gate (FN) transistors, wherein the word lines are denoted by WL, the control gates by CG, the bit lines of a byte having n bytes are denoted as BL[0:

n] and the common source lines for vertical bytes are denoted as source line (SL);

biasing for Erase and Erase-inhibit condition for selected page and selected bytes is performed by applying VPP1 voltage to WL and to CG, floating voltage to SL, and 0V to BL;

biasing for Erase and Erase inhibit operation for selected pages and unselected bytes is performed by applying VPP1 voltage to WL and to CG, floating voltage to SL and VPP2 voltage to BL;

biasing for Erase and Erase-inhibit condition for unselected pages and selected bytes is performed by applying VPP3 voltage to WL, floating voltage to SL, and 0V to BL and to CG; and

biasing for Erase and Erase-inhibit condition for unselected pages and unselected bytes is performed by applying VPP3 voltage to WL, floating voltage to SL, VPP2 voltage to BL, and 0V to CG;

wherein all the erase-Inhibit voltages are coupled from selected BLs to the channels of selected cells and keep their corresponding SLs floating to prevent the selected cells'"'"' channels from punch-through and wherein VPP1 is about 16V, VPP2 is about 6-16 V, and VPP3 is about 0-8V.

20. The two-transistor (2T) FLOTOX-based EEPROM cell array of claim 7, wherein a method to bias for Program and Program-Inhibit conditions of both positive and negative HV combination for the selected byte and the unselected bytes in the same selected WL during the FN program operation, comprising the select (ST) transistors and the floating gate (FN) transistors, wherein the word lines are denoted by WL, the control gates by CG, the bit lines of a byte having n bytes are denoted as BL[0:

n] and the common source lines for vertical bytes are denoted as source line (SL);

biasing for Program and Program-inhibit condition for selected page and selected bytes is performed by applying VPP1 voltage to WL, floating voltage to SL, VPP5 voltage to BL, and VNN1 voltage to CG;

biasing for Program and Program-Inhibit operation for selected page and unselected bytes is performed by applying VPP1 voltage to WL, floating voltage to SL and to BL, and VNN1 voltage to CG;

biasing for Program and Program-Inhibit condition for unselected pages and selected bytes is performed by applying VPP3 voltage to WL, floating voltage to SL, 0V to CG; and

VPP5 voltage to BL; and

biasing for Program and Program-Inhibit condition for unselected pages and unselected bytes is performed by applying VPP3 voltage to WL, floating voltage to SL and BL, and 0V to CG;

wherein all the Program-inhibit voltages are coupled from selected BLs to the channels of selected cells and keep their corresponding SLs floating to prevent the selected cells'"'"' channels from punch-through and wherein VPP1 is about 16V, VNN1=−

1-−

8V, VPP5=8V-10V, and VPP3 is about 0-8V.

21. The two-transistor (2T) FLOTOX-based EEPROM cell array of claim 7, wherein a method to bias for Erase and Erase-Inhibit conditions in unit of page comprising the select (ST) transistors and the floating gate (FN) transistors, wherein the word lines are denoted by WL, the control gates by CG, the bit lines of a byte having n bytes are denoted as BL[0:

n] and the common source lines for vertical bytes are denoted as source line (SL);

biasing for Erase and Erase-inhibit condition for selected page and selected bytes is performed by applying VPP3 voltage to WL, floating voltage to BL, 0V to SL, and VPP1 voltage to CG;

biasing for Erase and Erase inhibit operation for selected pages and unselected bytes is performed by applying VPP3 voltage to WL, VPP1 voltage to CG, floating voltage to BL, and VPP2 voltage to SL;

biasing for Erase and Erase-inhibit condition for unselected pages and selected bytes is performed by applying VPP3 voltage to WL, floating voltage to is BL, 0V to CG and to SL; and

biasing for Erase and Erase-inhibit condition for unselected pages and unselected bytes is performed by applying VPP3 voltage to WL, floating voltage to BL, VPP2 voltage to SL, and 0V to CG;

wherein the Erase-Inhibit voltages are coupled from the selected SLs and the corresponding BLs are left floating to prevent the selected cells'"'"' channels from punch-through and wherein VPP1 is about 15-18V, VPP2 is about 6-18 V, and VPP3 is about 0-8V.

22. The two-transistor (2T) FLOTOX-based EEPROM cell array of claim 7, wherein a method to bias for Program and Program-Inhibit conditions in unit of page comprising the select (ST) transistors and the floating gate (FN) transistors, wherein the word lines are denoted by WL, the control gates by CG, the bit lines of a byte having n bytes are denoted as BL[0:

n] and the common source lines for vertical bytes are denoted as source line (SL);

biasing for Program and Program-inhibit condition for selected page and selected bytes is performed by applying VPP1 voltage to WL and to BL, floating voltage to SL, and 0V voltage to CG;

biasing for Program and Program-Inhibit operation for selected page and unselected bytes is performed by applying VPP1 voltage to WL, floating voltage to SL and BL, and 0V voltage to CG;

biasing for Program and Program-Inhibit condition for unselected pages and selected bytes is performed by applying VPP3 voltage to WL, floating voltage to SL, 0V to CG; and

VPP1 voltage to BL; and

biasing for Program and Program-Inhibit condition for unselected pages and unselected bytes is performed by applying VPP3 voltage to WL, floating voltage to SL and BL, and 0V to CG;

wherein all the Program-Inhibit voltages are coupled from the selected SLs and the corresponding BLs are left floating to prevent the selected cells'"'"' channels from punch-through and wherein VPP1 is about 16V and VPP3 is about 0-8V.

32. The two-transistor FLOTOX-EEPROM cell array of claim 7, comprising (K+1) pages arranged in y-direction, each page comprising (N+1) bytes cascaded in x-direction wherein multiple pages can be selected or deselected.

33. The two-transistor (2T) FLOTOX-based EEPROM cell array of claim 32, wherein a method to bias for Erase condition for flexibly erasing the selected [K+1] pages, comprising the select (ST) transistors and the floating gate (FN) transistors, wherein the word lines are denoted by WL, the control gates by CG, the bit lines of a byte having n bytes are denoted as BL[0:

n] and the common source lines for vertical bytes are denoted as source line (SL);

biasing for Erase for selected page and selected bytes is performed by applying VPP1 voltage to WL and CG, floating voltage to SL, and 0V to BL;

biasing for Erase for unselected page and selected bytes is performed by applying VPP3 voltage to WL, floating voltage to SL, and 0V to CG and to BL;

wherein VPP1 is about 15-18V and VPP3 is about 0-8V.

23. A two-transistor (2T) FLOTOX-based EEPROM cell array comprising:

a matrix of a plurality of 2T FLOTOX EEPROM cells arranged in word-line circuits, which are arranged in rows and columns, each word line circuit comprising N+1 bytes, each EEPROM cell having one dedicated pair of vertical bit line and common source line connecting to respective drain and source and running perpendicular to WL and CG wherein each 2T-cell comprises;

a select transistor (ST); and

a floating gate Fowler-Nordheim (FN) transistor having a drain merged with a source of the associated select transistor;

said plurality of bit lines, each bit line associated with one column of the 2T FLOTOX EEPROM cells such that each bit line is connected to the drains of the 2T FLOTOX EEPROM cells of the associated column;

a plurality of vertical common source lines, each common source line associated with one column shared of the 2T FLOTOX EEPROM cells such that each source line is connected to the sources of the 2T FLOTOX EEPROM cells of the associated column;

a plurality of word lines, each word line associated with one row of the 2T FLOTOX EEPROM cells and connected to the gates of the select transistors of the associated row of two-transistor FLOTOX EEPROM cells and perpendicular to the bit lines and the source lines;

a plurality of common signal lines, each common signal line associated with one row of the 2T FLOTOX EEPROM cells and connected to the gates of the floating gate transistors of the associated row of two-transistor FLOTOX EEPROM cells and perpendicular to the bit lines and the source lines;

wherein no byte-select transistors and no global bit lines are needed and a whole page of the EEPROM array comprises multiple bytes cascaded in x-direction.

24. The two-transistor (2T) FLOTOX-based EEPROM cell array of claim 23, wherein a method to bias for Erase and Erase-Inhibit conditions in unit of page comprising the select (ST) transistors and the floating gate (FN) transistors, wherein the word lines are denoted by WL, the control gates by CG, the bit lines of a byte having n bytes are denoted as BL[0:

n] and the common source lines for vertical bytes are denoted as source line (SL);

biasing for Erase and Erase-inhibit condition for selected page and selected bytes is performed by applying VPP1 voltage to WL and to CG, floating voltage to SL, and 0V to BL;

biasing for Erase and Erase inhibit operation for selected pages and unselected bytes is performed by applying VPP1 voltage to WL and to CG, floating voltage to SL and VPP2 voltage to BL;

biasing for Erase and Erase-inhibit condition for unselected pages and selected bytes is performed by applying VPP3 voltage to WL, floating voltage to SL, and 0V to BL and CG; and

biasing for Erase and Erase-inhibit condition for unselected pages and unselected bytes is performed by applying VPP3 voltage to WL, floating voltage to SL, VPP2 voltage to BL, and 0V to CG;

wherein all the Erase-Inhibit voltages are coupled from selected BLs to the channels of selected cells and keep their corresponding SLs floating to prevent the selected cells'"'"' channels from punch-through and wherein VPP1 is about 15-18V, VPP2 is about 6-18 V, and VPP3 is about 0-8V.

25. The two-transistor (2T) FLOTOX-based EEPROM cell array of claim 23, wherein a method to bias for Program and Program-Inhibit conditions in unit of page comprising the select (ST) transistors and the floating gate (FN) transistors, wherein the word lines are denoted by WL, the control gates by CG, the bit lines of a byte having n bytes are denoted as BL[0:

n] and the common source lines for vertical bytes are denoted as source line (SL);

biasing for Program and Program-inhibit condition for selected page and selected bytes is performed by applying VPP1 voltage to WL and to BL, VPP4 voltage to SL, and 0V to CG;

biasing for Program and Program-Inhibit operation for selected page and unselected bytes is performed by applying VPP1 voltage to WL, floating voltage to BL, VPP4 voltage to SL, and 0V to CG;

biasing for Program and Program-Inhibit condition for unselected pages and selected bytes is performed by applying VPP3 voltage to WL, VPP4 voltage to SL, 0V to CG, and VPP1 voltage to BL; and

biasing for Program and Program-Inhibit condition for unselected pages and unselected bytes is performed by applying VPP3 voltage to WL, floating voltage to BL, VPP4 voltage to SL, and 0V to CG;

wherein all the Program-Inhibit voltages are coupled from selected BLs to the channels of selected cells and keep their corresponding SLs floating to prevent the selected cells'"'"' channels from punch-through and wherein VPP1 is about 15-18V, VPP3 is about 0-8V, and VPP4 is about 0-8V.

26. The two-transistor (2T) FLOTOX-based EEPROM cell array of claim 23, wherein a method to bias for Erase and Erase-Inhibit conditions in unit of page comprising the select (ST) transistors and the floating gate (FN) transistors, wherein the word lines are denoted by WL, the control gates by CG, the bit lines of a byte having n bytes are denoted as BL[0:

n] and the common source lines for vertical bytes are denoted as source line (SL);

biasing for Erase and Erase-inhibit condition for selected page and selected bytes is performed by applying VPP3 voltage to WL, floating voltage to BL and SL, and VPP1 voltage to CG;

biasing for Erase and Erase inhibit operation for selected pages and unselected bytes is performed by applying VPP3 voltage to WL, VPP1 voltage to CG, floating voltage to BL, and VPP2 voltage to SL;

biasing for Erase and Erase-inhibit condition for unselected pages and selected bytes is performed by applying VPP3 voltage to WL, floating voltage to BL and SL, and 0V to CG; and

biasing for Erase and Erase-inhibit condition for unselected pages and unselected bytes is performed by applying VPP3 voltage to WL, floating voltage to BL, VPP2 voltage to SL, and 0V to CG;

wherein the Erase-Inhibit voltages are coupled from the selected SLs and the corresponding BLs are left floating to prevent the selected cells'"'"' channels from punch-through and wherein VPP1 is about 16V, VPP2 is about 6-16 V, and VPP3 is about 0-8V.

27. The two-transistor (2T) FLOTOX-based EEPROM cell array of claim 23, wherein a method to bias for Program and Program-Inhibit conditions in unit of page comprising the select (ST) transistors and the floating gate (FN) transistors, wherein the word lines are denoted by WL, the control gates by CG, the bit lines of a byte having n bytes are denoted as BL[0:

n] and the common source lines for vertical bytes are denoted as source line (SL);

biasing for Program and Program-inhibit condition for selected page and selected bytes is performed by applying VPP1 voltage to WL and to BL, floating voltage to SL, and 0V voltage to CG;

biasing for Program and Program-Inhibit operation for selected page and unselected bytes is performed by applying VPP1 voltage to WL, floating voltage to SL and BL, and 0V voltage to CG;

biasing for Program and Program-Inhibit condition for unselected pages and selected bytes is performed by applying VPP3 voltage to WL, floating voltage to SL, 0V to CG; and

VPP1 voltage to BL; and

biasing for Program and Program-Inhibit condition for unselected pages and unselected bytes is performed by applying VPP3 voltage to WL, floating voltage to SL and BL, and 0V to CG;

wherein all the Program-Inhibit voltages are coupled from the selected SLs and the corresponding BLs are left floating to prevent the selected cells'"'"' channels from punch-through and wherein VPP1 is about 16V, and VPP3 is about 0-8V.

28. The two-transistor (2T) FLOTOX-based EEPROM cell array of claim 23, wherein a method to bias for Erase and Erase-Inhibit conditions in unit of page comprising the select (ST) transistors and the floating gate (FN) transistors, wherein the word lines are denoted by WL, the control gates by CG, the bit lines of a byte having n bytes are denoted as BL[0:

n] and the common source lines for vertical bytes are denoted as source line (SL);

biasing for Erase and Erase-inhibit condition for selected page and selected bytes is performed by applying VPP1 voltage to WL and BL, floating voltage to SL, and 0V to CG;

biasing for Erase and Erase inhibit operation for selected pages and unselected bytes is performed by applying VPP1 voltage to WL, 0V to CG, and floating voltage to SL and to BL;

biasing for Erase and Erase-inhibit condition for unselected pages and selected bytes is performed by applying VPP3 voltage to WL, floating voltage to SL, VPP1 voltage to BL, and 0V to CG; and

biasing for Erase and Erase-inhibit condition for unselected pages and unselected bytes is performed by applying VPP3 voltage to WL, floating voltage to BL and to SL, and 0V to CG;

wherein the Erase-Inhibit voltages are coupled from the selected SLs and the corresponding BLs are left floating to prevent the selected cells'"'"' channels from punch-through and wherein VPP1 is about 16V and VPP3 is about 0-8V.

29. The two-transistor (2T) FLOTOX-based EEPROM cell array of claim 23, wherein a method to bias for Program and Program-Inhibit conditions in unit of page comprising the select (ST) transistors and the floating gate (FN) transistors, wherein the word lines are denoted by WL, the control gates by CG, the bit lines of a byte having n bytes are denoted as BL[0:

n] and the common source lines for vertical bytes are denoted as source line (SL);

biasing for Program and Program-inhibit condition for selected page and selected bytes is performed by applying VPP1 voltage to WL and to CG, floating voltage to SL, and 0V voltage to BL;

biasing for Program and Program-Inhibit operation for selected page and unselected bytes is performed by applying VPP1 voltage to WL and to CG, floating voltage to SL, and VPP2 voltage to BL;

biasing for Program and Program-Inhibit condition for unselected pages and selected bytes is performed by applying VPP3 voltage to WL, floating voltage to SL, 0V to CG and to BL; and

biasing for Program and Program-Inhibit condition for unselected pages and unselected bytes is performed by applying VPP3 voltage to WL, floating voltage to SL, VPP2 voltage to BL and 0V to CG,

wherein the Program-Inhibit voltages are coupled from the selected SLs and the corresponding BLs are left floating to prevent the selected cells'"'"' channels from punch-through and wherein VPP1 is about 16V, VPP2 is about 8-16V, and VPP3 is about 0-8V.

30. The two-transistor (2T) FLOTOX-based EEPROM cell array of claim 23, wherein a method to bias for Erase and Erase-Inhibit conditions in unit of single bit comprising the select (ST) transistors and the floating gate (FN) transistors, wherein the word lines are denoted by WL, the control gates by CG, the bit lines of a byte having n bytes are denoted as BL[0:

n] and the common source lines for vertical bytes are denoted as source line (SL);

biasing for Erase and Erase-inhibit condition for selected page and selected bytes is performed by applying VPP1 voltage to WL and to CG, floating voltage to SL, and 0V to BL;

biasing for Erase and Erase inhibit operation for selected pages and unselected bytes is performed by applying VPP1 voltage to WL and CG, VPP2 voltage to BL, and floating voltage to SL;

biasing for Erase and Erase-inhibit condition for unselected pages and selected bytes is performed by applying VPP3 voltage to WL, floating voltage to is SL, and 0V to BL and CG; and

biasing for Erase and Erase-inhibit condition for unselected pages and unselected bytes is performed by applying VPP3 voltage to WL, floating voltage to SL, VPP2 voltage to SL, and 0V to CG;

wherein the Erase-Inhibit voltages are coupled from the selected SLs and the corresponding BLs are left floating to prevent the selected cells'"'"' channels from punch-through and wherein VPP1 is about 15-18V, VPP2 is about 6-18V, and VPP3 is about 0-8V.

31. The two-transistor (2T) FLOTOX-based EEPROM cell array of claim 23, wherein a method to bias for Program and Program-Inhibit conditions in unit of bit comprising the select (ST) transistors and the floating gate (FN) transistors, wherein the word lines are denoted by WL, the control gates by CG, the bit lines of a byte having n bytes are denoted as BL[0:

n] and the common source lines for vertical bytes are denoted as source line (SL);

biasing for Program and Program-inhibit condition for selected page and selected bytes is performed by applying VPP1 voltage to WL and to BL, floating voltage to SL, and 0V voltage to CG;

biasing for Program and Program-Inhibit operation for selected page and unselected bytes is performed by applying VPP1 voltage to WL, floating voltage to SL and BL, and 0V voltage to CG;

biasing for Program and Program-Inhibit condition for unselected pages and selected bytes is performed by applying VPP3 voltage to WL, floating voltage is to SL, 0V to CG; and

VPP1 voltage to BL; and

biasing for Program and Program-Inhibit condition for unselected pages and unselected bytes is performed by applying VPP3 voltage to WL, floating voltage to SL and BL, and 0V to CG;

wherein all the Program-Inhibit voltages are coupled from the selected SLs and the corresponding BLs are left floating to prevent the selected cells'"'"' channels from punch-through and wherein VPP1 is about 15-18V and VPP3 is about 0-8V.

34. The two-transistor (2T) FLOTOX-based EEPROM cell array of claim 23, comprising (K+1) pages arranged in y-direction, each page comprising (N+1) bytes cascaded in x-direction wherein multiple pages can be selected or deselected.

35. The two-transistor (2T) FLOTOX-based EEPROM cell array of claim 34, wherein a method to bias for Erase condition for flexibly erasing any number of selected blocks and pages without inducing the disturbance to the unselected pages and blocks to drastically reduce the erase time, comprising the select (ST) transistors and the floating gate (FN) transistors, wherein the word lines are denoted by WL, the control gates by CG, the bit lines of a byte having n bytes are denoted as BL[0:

n] and the common source lines for vertical bytes are denoted as source line (SL);

biasing for Erase for selected page and selected bytes is performed by applying VPP1 voltage to WL and CG, floating voltage to SL, and 0V to BL;

biasing for Erase for unselected page and selected bytes is performed by applying VPP3 voltage to WL, floating voltage to SL, and 0V to CG and to BL;

wherein VPP1 is about 15-18V and VPP3 is about 0-8V.

36. A combination of a hybrid FLOTOX-based EEPROM memory and a Flotox-based NOR Flash memory array integrated for data and code storages within one IC chip, wherein the byte pitch of NOR Flash memory can be kept identical with the byte-pitch of EEPROM memory and therefore, in the physical array layout, EEPROM and NOR Flash memory can be placed on top of each other with perfect match in x-direction and wherein every single byte of each page of the NOR flash memory array does not need one GBL for byte-alterable data storage as the page of NOR Flash array for the block-alterable code storage and wherein the combination comprises one common X-decoder and one common page buffer.

37. The combination of a hybrid FLOTOX-based EEPROM memory and a Flotox-based NOR Flash memory array of claim 36 wherein a flexible partition can be implemented between both memory arrays.

38. The combination of a hybrid FLOTOX-based EEPROM memory and a Flotox-based NOR Flash memory array of claim 36 wherein said x-decoder has three level of decoding scheme wherein the logic of the X-decoder design allows the selection of flexible number of word lines to be selected for erase operation to save the erase time drastically wherein the number of word lines can be flexibly selected for erase is set to be 2ⁿ, where n value is set to be 1 to 3 for each block.

39. The combination of a hybrid FLOTOX-based EEPROM memory and a Flotox-based NOR Flash memory array of claim 36 wherein both NOR and EEPROM comprising a plurality of sectors, each sector further comprising a plurality of pages and each page comprising a plurality of bytes, each byte preferably comprising eight vertical BLs and one shared horizontal SL without a global bit line (GBL).

40. The combination of a hybrid FLOTOX-based EEPROM memory and a Flotox-based NOR Flash memory array of claim 36 wherein both NOR and EEPROM comprising a plurality of sectors, each sector further comprising a plurality of pages and each page comprising a plurality of bytes, each byte preferably comprising eight vertical BLs and one shared horizontal SL with a global bit line (GBL).

41. The combination of a hybrid FLOTOX-based EEPROM memory and a Flotox-based NOR Flash memory array of claim 36 wherein both NOR and EEPROM comprising a plurality of sectors, each sector further comprising a plurality of pages and each page comprising a plurality of bytes, each byte preferably comprising eight vertical BLs and eight vertical SLs with a global bit line (GBL).

42. The combination of a hybrid FLOTOX-based EEPROM memory and a Flotox-based NOR Flash memory array of claim 36 wherein both NOR and EEPROM comprising a plurality of sectors, each sector further comprising a plurality of pages and each page comprising a plurality of bytes, each byte preferably comprising eight vertical BLs and eight vertical SLs without a global bit line (GBL).