ALLOCATION OF MEMORY BUFFERS BASED ON PREFERRED MEMORY PERFORMANCE

• US 20120066471A1
• Filed: 11/22/2011
• Published: 03/15/2012
• Est. Priority Date: 09/14/2010
• Status: Active Application

• Current Assignee: Advanced Micro Devices, Inc.
• Original Assignee: Advanced Micro Devices, Inc.
• Inventors: Rogers, Philip J., Iourcha, Konstantine I., Sadowski, Greg, Kruger, W. Fritz, BROTHERS, III, John Wakefield
• Application Number:
  US13/302,499
• Publication Number:
  US 20120066471A1
• Time in Patent Office: Days
• US Class Current: 711/172
• CPC Class Codes: G06F 13/1673 using buffers
• CPC Class Codes: G06F 13/1684 using multiple buses
• CPC Class Codes: Y02D 10/00 Energy efficient computing, e.g. low power processors, power management or thermal management

Abstract

A method and system are provided for associating one or more memory buffers in a computing system with a plurality of memory channels. The method and apparatus associates one or more memory buffers with a plurality of memory banks based on preferred performance settings, wherein the plurality of memory banks spans over one or more of the plurality of memory channels. Additionally, the method and apparatus accesses the one or more memory buffers based on the preferred performance settings. Further, the method and apparatus can, in response to accessing the one or more memory buffers based on the preferred performance settings, determine whether the preferred performance settings are being satisfied.

Claims

1. A method for associating one or more memory buffers in a computing system with a plurality of memory channels, the method comprising:

associating one or more memory buffers with a plurality of memory banks based on preferred performance settings, wherein the plurality of memory banks spans over one or more of the plurality of memory channels; and

accessing the one or more memory buffers based on the preferred performance settings.

2. The method of claim 1, further comprising:

in response to accessing the one or more memory buffers based on the preferred performance settings, determining whether the preferred performance settings are being satisfied.

3. The method of claim 2, wherein determining whether the preferred performance settings are being satisfied comprises comparing tracking information with the preferred performance settings, wherein tracking information comprises at least one of:

bandwidth usage information indicating a bandwidth at which the one or more memory buffers are operating at during operation of the computing system;

latency information indicating a latency associated with the one or more memory buffers during operation of the computing system; and

memory client access information indicating which one or more memory clients have accessed each of the one or more memory buffers.

4. The method of claim 2, further comprising:

in response to determining that the preferred performance settings are not being satisfied, adjusting at least one of a clock frequency associated with one or more of the plurality of memory channels and a voltage associated with one or more of the plurality of memory channels based on the preferred performance settings.

5. The method of claim 2, further comprising:

in response to determining that the preferred performance settings are not being satisfied, re-associating the one or more memory buffers to a different plurality of memory banks based on the preferred performance settings.

6. The method of claim 1, wherein the preferred performance settings are provided by a memory client operative to access the one or more memory buffers.

7. The method of claim 6, wherein the preferred performance settings comprise at least one of:

a preferred bandwidth of the one or more memory buffers;

a preferred latency associated with the one or more memory buffers; and

a listing of different one or more memory clients operative to access the same one or more memory buffers as the memory client.

8. The method of claim 6, wherein the memory client comprises at least one of a computing device and a software application.

9. The method of claim 1, wherein associating one or more memory buffers comprises setting a channel mapping policy, wherein the channel mapping policy describes whether at least one of a user and a kernel may access the one or more memory buffers.

10. A computing system, comprising:

a plurality of memory channels, the plurality of memory channels comprising a respective plurality of memory devices;

memory management logic operative to generate association information based on preferred performance settings; and

one or more memory controllers operatively connected to the plurality of memory channels and the memory management logic, the one or more memory controllers operative to;

in response to receiving association information from the memory management logic, associate one or more memory buffers with a plurality of memory banks based on the preferred performance settings, wherein the plurality of memory banks spans over one or more of the plurality of memory channels.

11. The computing system of claim 10, wherein the one or more memory controllers comprise preferred performance settings monitoring logic operative to generate tracking information, the tracking information comprising at least one of:

bandwidth usage information indicating a bandwidth at which the one or more memory buffers are operating at during operation of the computing system;

latency information indicating a latency associated with the one or more memory buffers during operation of the computing system; and

memory client access information indicating which one or more memory clients have accessed each of the one or more memory buffers.

12. The computing system of claim 11, wherein the memory management logic comprises preferred performance settings comparison logic, the preferred performance settings comparison logic operative to determine whether the preferred performance settings are being satisfied by comparing the tracking information with the preferred performance settings.

13. The computing system of claim 12, wherein the memory management logic further comprises association and adjustment logic operatively connected to the preferred performance settings comparison logic, the association and adjustment logic operative to generate adjustment information in response to a determination by the preferred performance settings comparison logic that the preferred performance settings are not being satisfied.

14. The computing system of claim 13, wherein, in response to receiving adjustment information, the one or more memory controllers are operative to make at least one of the following adjustments:

adjusting a clock frequency associated with one or more of the plurality of memory channels;

adjusting a voltage associated with one or more of the plurality of memory channels; and

re-associating the one or more memory buffers to a different plurality of memory banks based on the preferred performance settings.

15. The computing system of claim 10, wherein the preferred performance settings are provided to the memory management logic by a memory client operative to access the one or more memory buffers.

16. The computing system of claim 15, wherein the preferred performance settings comprise at least one of:

a preferred bandwidth of the one or more memory buffers;

a preferred latency of associated with the one or more memory buffers; and

a listing of different one or more memory clients operative to access the same one or more memory buffers as the memory client.

17. The computing system of claim 15, wherein the memory client comprises at least one of a computing device and a software application.

18. The computing system of claim 10, wherein, in response to receiving association information from the memory management logic, the one or more memory controllers are operative to set a channel mapping policy, wherein the channel mapping policy describes whether at least one of a user and a kernel may access the one or more memory buffers.

19. The computing system of claim 10, further comprising:

a plurality of data buses that correspond to the plurality of memory devices, wherein the plurality of data buses is operative to transfer data between the one or more memory controllers and the respective plurality of memory devices.