Computing Device with Asynchronous Auxiliary Execution Unit

• US 20120066483A1
• Filed: 09/15/2010
• Published: 03/15/2012
• Est. Priority Date: 09/15/2010
• Status: Active Grant

• Current Assignee: International Business Machines Corporation
• Original Assignee: International Business Machines Corporation
• Inventors: Mitchell, Michael Bryan, Steinmetz, Paul Michael, Tsuchiya, Kenichi, Boury, Bechara F.
• Granted Patent: US 9,201,801 B2
• Time in Patent Office: Days
• US Class Current: 712/233
• CPC Class Codes: G06F 12/0875 with dedicated cache, e.g. instruction or stack
• CPC Class Codes: G06F 9/382 Pipelined decoding, e.g. using predecoding
• CPC Class Codes: G06F 9/3836 Instruction issuing, e.g. dynamic instruction scheduling or out of order instruction execution
• CPC Class Codes: G06F 9/3854 Instruction completion, e.g. retiring, committing or graduating
• CPC Class Codes: G06F 9/3856 Reordering of instructions, e.g. using queues or age tags
• CPC Class Codes: G06F 9/3858 Result writeback, i.e. updating the architectural state or memory
• CPC Class Codes: G06F 9/3861 Recovery, e.g. branch miss-prediction, exception handling error detection or correction G06F11/00
• CPC Class Codes: G06F 9/3877 using a slave processor, e.g. coprocessor peripheral processor G06F13/12; vector processor G06F15/8053
• CPC Class Codes: G06F 9/3885 using a plurality of independent parallel functional units
• CPC Class Codes: G06F 9/3889 controlled by multiple instructions, e.g. MIMD, decoupled access or execute

Abstract

A computing device includes: an instruction cache storing primary execution unit instructions and auxiliary execution unit instructions in a sequential order; a primary execution unit configured to receive and execute the primary execution unit instructions from the instruction cache; an auxiliary execution unit configured to receive and execute only the auxiliary execution unit instructions from the instruction cache in a manner independent from and asynchronous to the primary execution unit; and completion circuitry configured to coordinate completion of the primary execution unit instructions by the primary execution unit and the auxiliary execution unit instructions according to the sequential order.

Claims

1. A computing device comprising:

an instruction cache comprising primary execution unit instructions and auxiliary execution unit instructions in a sequential order;

a primary execution unit configured to receive and execute said primary execution unit instructions from said instruction cache;

an auxiliary execution unit configured to receive and execute only said auxiliary execution unit instructions from said instruction cache in a manner independent from and asynchronous to said primary execution unit; and

completion circuitry configured to coordinate completion of said primary execution unit instructions by said primary execution unit and said auxiliary execution unit instructions according to said sequential order.

2. The computing device of claim 1, further comprising predecode circuitry configured to:

attach predecode bits to each said instruction stored into said instruction cache, said predecode bits indicating at least whether said instruction is a said auxiliary execution unit instruction.

3. The computing device of claim 1, said auxiliary execution unit further comprising an instruction queue comprising a plurality of storage positions, each said storage position in said instruction queue storing a said received auxiliary execution unit instruction while preserving an order in which said auxiliary execution unit instructions were received from said instruction cache.

4. The computing device of claim 3, further comprising control circuitry configured to identify said auxiliary execution unit instructions in said instruction cache and send a number of said auxiliary execution unit instructions in said instruction cache to said auxiliary execution unit based on a signal from said auxiliary execution unit indicating available space in said instruction queue of said auxiliary execution unit.

5. The computing device of claim 3, said auxiliary execution unit further comprising circuitry configured to implement a plurality of execution pipelines and circuitry configured to associate each of a number of oldest auxiliary execution unit instructions in said instruction queue with one of said execution pipelines.

6. The computing device of claim 5, said auxiliary execution unit further comprising circuitry configured to issue each of said number of oldest auxiliary execution instructions in said instruction queue to said execution pipeline associated with said auxiliary execution instruction in response to a determination that said execution pipeline associated with said auxiliary execution instruction is available.

7. The computing device of claim 5, said auxiliary execution unit being further configured to perform out-of-order execution on said number of oldest auxiliary execution instructions in said instruction queue.

8. The computing device of claim 3, further comprising circuitry configured to provide an electronic indication to said auxiliary execution unit of a mispredicted branch in said computing device.

9. The computing device of claim 8, said auxiliary execution unit being further configured to identify and flush any said auxiliary execution instruction being stored or executed by said auxiliary execution unit that is more recent than said mispredicted branch

10. The computing device of claim 3, further comprising:

a commit bit associated with each said auxiliary execution unit instruction in said instruction queue; and

circuitry configured to set said commit bit for a selected auxiliary execution unit instruction in a said storage position in said instruction queue responsive to a determination that each said auxiliary execution unit instruction in said instruction queue that is older than said selected auxiliary execution unit instruction either has a set commit bit or is storing a said auxiliary execution unit instruction that has been determined to not cause any hardware exceptions in said computing device.

11. The computing device of claim 10, said control circuitry being further configured to coordinate completion of said auxiliary execution unit instructions based on said commit bits associated with said instruction queue.

12. A computing device, comprising:

a memory storing a series of digitally encoded fixed-point instructions and floating point instructions in a sequential order;

an instruction cache storing a subset of said fixed-point instructions and said floating point instructions stored by said memory;

a fixed-point execution unit and a floating point execution unit operative such that a receipt and execution of said fixed-point instructions by said fixed-point execution unit is asynchronous to a receipt and execution of said floating point instructions by said floating point execution unit; and

control circuitry configured to coordinate completion of said fixed-point instructions and said floating point instructions by said fixed-point execution unit and said floating point execution unit instructions according to said sequential order.

13. The computing device of claim 12, further comprising predecode circuitry disposed between said memory and said instruction cache, said predecode circuitry being configured to:

attach predecode bits to each said fixed-point instruction and each said instruction stored by said instruction cache, said predecode bits indicating at least whether said instruction is a said floating point instruction.

14. The computing device of claim 12, said floating point execution unit further comprising an instruction queue comprising a plurality of storage positions, each said storage position in said instruction queue storing a said floating instruction received from said instruction cache while preserving an order in which said floating point instructions were received from said instruction cache.

15. The computing device of claim 14, further comprising circuitry that identifies said floating point instructions in said instruction cache and sends a number of said floating point instructions in said instruction cache to said floating point execution unit based on a signal from said floating point execution unit indicating available space in said instruction queue of said floating point execution unit.

16. The computing device of claim 14, said floating point execution unit being further configured to perform out-of-order execution on said number of oldest floating point instructions in said instruction queue.

17. The computing device of claim 12, further comprising circuitry that provides an electronic indication to said floating point execution unit of a mispredicted branch in said computing device.

18. The computing device of claim 17, said floating point execution unit being further configured to identify and flush any said floating point instruction being stored or executed by said floating point execution unit that is newer than said mispredicted branch

19. The computing device of claim 12, further comprising:

a commit bit associated with each said floating point instruction in said instruction queue of said floating point execution unit; and

circuitry that sets said commit bit for a selected floating point instruction in a said storage position in said instruction queue responsive to a determination that each said floating point instruction in said instruction queue that is older than said selected floating point instruction either has a set commit bit or is storing a said floating point instruction that has been determined to not cause any hardware exceptions in said computing device.

20. The computing device of claim 19, wherein said control circuitry is configured to coordinate completion of said floating point instructions based on said commit bits.

21. A method of controlling execution unit operations in a computer device, comprising:

storing computer instructions in a memory according to a sequential order;

caching at least a subset of said computer instructions in an instruction cache;

classifying each said computer instructions in said instruction cache as at least one of a primary execution unit instruction and an auxiliary execution unit instruction;

asynchronously providing said primary execution unit instructions to a primary execution unit and said auxiliary execution unit instructions to an auxiliary execution unit;

asynchronously executing said primary execution unit instructions and said auxiliary execution unit instructions in said primary execution unit and said auxiliary execution unit, respectively; and

controlling said primary execution unit and said auxiliary execution unit such that said primary execution unit instructions and said auxiliary execution unit instructions are completed synchronously according to said sequential order.

22. The method of claim 21, further comprising providing an electronic indication to said auxiliary execution unit of a mispredicted branch.

23. The method of claim 22, further comprising identifying and flushing any said auxiliary execution instruction being stored or executed by said auxiliary execution unit that is newer than said mispredicted branch.

24. The method of claim 22, said electronic indication to said auxiliary execution unit of a mispredicted branch comprising a timing frequency that is substantially equal to a timing frequency of commit signals provided to said primary execution unit and said auxiliary execution unit to control completion of said primary execution unit instructions and said auxiliary execution unit instructions.

25. A computer system comprising:

a memory device having computer-readable program code stored thereon, said computer-readable program code comprising a series of digitally encoded fixed-point instructions and floating point instruction in sequential order; and

a processor, said processor comprising;

an instruction cache storing a subset of said fixed-point instructions and said floating point instructions stored by said memory;

a fixed-point execution unit and a floating point execution unit operative such that a receipt and execution of said fixed-point instructions by said fixed-point execution unit is asynchronous to a receipt and execution of said floating point instructions by said floating point execution unit; and

control circuitry configured to coordinate completion of said fixed-point instructions and said floating point instructions by said fixed-point execution unit and said floating point execution unit instructions according to said sequential order.