DATA PROCESSING SYSTEM HAVING END-TO-END ERROR CORRECTION AND METHOD THEREFOR

• US 20120066567A1
• Filed: 09/13/2010
• Published: 03/15/2012
• Est. Priority Date: 09/13/2010
• Status: Active Grant

• Current Assignee: North Star Innovations Inc. (Wi-LAN Inc.)
• Original Assignee: Freescale Semiconductor, Inc. (NXP Semiconductors NV)
• Inventors: MOYER, WILLIAM C.
• Granted Patent: US 8,990,660 B2
• Time in Patent Office: Days
• US Class Current: 714/763
• CPC Class Codes: G06F 11/1048 using arrangements adapted for a specific error detection or correction feature
• CPC Class Codes: G06F 11/1076 Parity data used in redundant arrays of independent storages, e.g. in RAID systems

Abstract

In a data processing system having a plurality of error coding function circuitries, a method includes receiving an address which indicates a first storage location for storing a first data value; using a first portion of the address to select one of the plurality of error coding function circuitries as a selected error coding function circuitry; and using the selected error coding function circuitry to generate a first checkbit value, wherein the selected error coding function circuitry uses the first data value to generate the first checkbit value. When the first portion of the address has a first value, a first one of the plurality of error coding function circuitries is selected as the selected error coding function circuitry. When the first portion of the address has a second value, a second one of the plurality of error coding function circuitries is selected as the selected error coding function circuitry.

Claims

1. In a data processing system having a plurality of error coding function circuitries, each implementing a different coding function, a method for generating a checkbit value, the method comprising:

receiving an address which indicates a first storage location for storing a first data value;

using a first portion of the address to select one of the plurality of error coding function circuitries as a selected error coding function circuitry, wherein;

when the first portion of the address has a first value, selecting a first one of the plurality of error coding function circuitries as the selected error coding function circuitry, and

when the first portion of the address has a second value, different from the first value, selecting a second one of the plurality of error coding function circuitries as the selected error coding function circuitry; and

using the selected error coding function circuitry to generate a first checkbit value, wherein the selected error coding function circuitry uses the first data value to generate the first checkbit value.

2. The method of claim 1, wherein the selected error coding function circuitry uses the first data value and a second portion of the address to generate the first checkbit value.

3. The method of claim 2, wherein the first portion of the address is further characterized as a more significant portion of the address than the second portion of the address.

4. The method of claim 2, wherein the second portion of the address does not include the first portion of the address.

5. The method of claim 1, further comprising:

storing the first data value and the first checkbit value.

6. The method of claim 5, further comprising:

receiving a second address which indicates a second storage location for storing a second data value;

using a first portion of the second address to select another one of the plurality of error coding function circuitries as a second selected error coding function circuitry;

using the second selected error coding function circuitry to generate a second checkbit value, wherein the second selected error coding function circuitry uses the second data value to generate the second checkbit value;

storing the second data value and the second checkbit value;

accessing the stored first data value, first checkbit value, second data value, and second checkbit value;

transforming the first checkbit value and the second checkbit value into a third checkbit value which has a granularity to cover both the first and the second data value; and

storing the first data value concatenated with the second data value and the third checkbit value in a third storage location.

7. The method of claim 6, further comprising:

transferring the first data value concatenated with a second data value over a system interconnect and using the third checkbit value to perform end to end error detection of the first data value concatenated with a second data value.

8. The method of claim 6, wherein the step of transforming comprises:

performing a bit-wise exclusive OR of the first checkbit value with the second checkbit value to obtain the third checkbit value.

9. The method of claim 6, wherein the step of transforming comprises:

performing a bit-wise exclusive OR of the first checkbit value with the second checkbit value to obtain a fourth checkbit value based on the first data value concatenated with the second data value;

providing a second portion of the address to address error coding function circuitry to generate a fifth checkbit value based on the second portion of the address; and

performing a bit-wise exclusive OR of the fourth checkbit value with the fifth checkbit value to obtain the third checkbit value.

10. In a data processing system having a processor and a memory coupled to the processor via a system interconnect, a method comprising:

initiating a read operation of a memory location;

in response to the initiating the read operation, receiving a first data value and a first checkbit value corresponding to the first data value from the memory location, wherein the first data value comprises a first data value portion and a second data value portion, each of the first and second data value portions having fewer bits than the first data value;

providing the first checkbit value to first transforming circuitry and to second transforming circuitry, wherein the first transforming circuitry generates a second checkbit value corresponding to the first data value portion and the second transforming circuitry generates a third checkbit value corresponding to the second data value portion; and

storing the first data value portion with the second checkbit value in a first storage location and storing the second data value portion with the third checkbit value in a second storage location.

11. The method of claim 10, further comprising:

accessing the first data value portion and the second checkbit value; and

using the second checkbit value and not the first checkbit value to check the first data value portion.

12. The method of claim 10, further comprising:

in response to the step of initiating the read operation, the memory providing the first data value and the second checkbit value to the processor via the system interconnect; and

after the step of receiving the first data value and the second checkbit value and prior to the step of providing the first checking value to the first transforming circuitry and the second transforming circuitry, performing, by the processor, end to end error detection by using the first checkbit value to check the first data value.

13. The method of claim 10, wherein each of the first and second storage locations are located within a cache memory of the processor and the memory location is located in the memory, and wherein the step of initiating the read operation is performed in response to a cache miss or a cache fill.

14. The method of claim 13, wherein:

the first transforming circuitry uses system error coding function circuitry for generating a checkbit value for an N-bit data value, first internal error coding function circuitry for generating a checkbit value for an M-bit data value, and cache index error coding function circuitry for generating a checkbit value for a cache index of the cache;

the second transforming circuitry uses the system error coding function circuitry, second internal error coding function circuitry for generating a checkbit value for the M-bit data value, and the cache index error coding function circuitry; and

the second internal error coding function circuitry implements a different coding function than the first internal error coding function and N is greater than M, the first data value being an N-bit data value and each of the first and second data value portions being the M-bit data value.

15. The method of claim 10, wherein:

the first transforming circuitry uses system error coding function circuitry for generating a checkbit value for an N-bit data value and first internal error coding function circuitry for generating a checkbit value for an M-bit data value;

the second transforming circuitry uses the system error coding function circuitry and second internal error coding function circuitry for generating a checkbit value for an M-bit data value; and

the second internal error coding function circuitry implements a different coding function that the first internal error coding function and N is greater than M, the first data value being an N-bit data value and each of the first and second data value portions being an M-bit data value.

16. The method of claim 15, wherein:

the system error coding function circuitry comprises a first plurality of exclusive OR (XOR) gates, wherein each XOR gate of the first plurality of XOR gates outputs one corresponding bit value of the first checkbit value, and wherein each XOR gate of the first plurality of XOR gates receives a predetermined subset of bit values of the first data value;

the first internal error coding function circuitry comprises a second plurality of XOR gates, wherein each XOR gate of the second plurality of XOR gates outputs one corresponding bit value of the third checkbit value, and wherein each XOR gate of the second plurality of XOR gates receives a predetermined subset of bit values of the second data value portion; and

the second internal error coding function circuitry comprises a third plurality of XOR gates, wherein each XOR gate of the third plurality of XOR gates outputs one corresponding bit value of the second checkbit value, and wherein each XOR gate of the third plurality of XOR gates receives a predetermined subset of bit values of the first data value portion.

17. In a data processing system having a processor and a memory coupled to the processor via a system interconnect, a method comprising:

accessing a cache of the processor to access a first storage location and an adjacent second storage location, wherein the first storage location comprises a first data value and a first checkbit value corresponding to the first data value and the second storage location comprises a second data value and a second checkbit value corresponding to the second data value;

transforming the first checkbit value and the second checkbit value into a third checkbit value which has a granularity to cover the first data value combined with the second data value; and

storing the first data value concatenated with the second data value and the third checkbit value in a storage location of the memory.

18. The method of claim 17, further comprising:

transferring the first data value concatenated with the second data value over the system interconnect from the memory to the processor; and

using the third checkbit value to perform end to end error detection of the first data value concatenated with the second data value.

19. The method of claim 17, wherein the step of transforming comprises:

performing a bit-wise exclusive OR (XOR) of the first checkbit value with the second checkbit value to obtain the third checkbit value.

20. The method of claim 17, wherein the step of transforming comprises:

performing a bit-wise XOR of the first checkbit value with the second checkbit value to obtain a fourth checkbit value based on the first data value concatenated with the second data value;

providing a second portion of the address to address error coding function circuitry to generate a fifth checkbit value based on the second portion of the address; and

performing a bit-wise exclusive OR of the fourth checkbit value with the fifth checkbit value to obtain the third checkbit value.