STORAGE DEVICE, ELECTRONIC DEVICE, AND DATA ERROR CORRECTION METHOD

• US 20120066568A1
• Filed: 06/13/2011
• Published: 03/15/2012
• Est. Priority Date: 09/14/2010
• Status: Active Grant

• Current Assignee: Kabushiki Kaisha Toshiba (Toshiba Corporation)
• Original Assignee: Kabushiki Kaisha Toshiba (Toshiba Corporation)
• Inventors: KOMAGOME, Yutaka
• Granted Patent: US 8,671,330 B2
• Time in Patent Office: Days
• US Class Current: 714/764
• CPC Class Codes: G06F 11/1016 Error in accessing a memory location, i.e. addressing error

Abstract

According to one embodiment, a storage device includes an error detector, a check module, and a replacement module. The error detector detects a bit error that occurs in entry data related to conversion to a physical address corresponding to a logical address based on an error detecting code assigned to the entry data. The check module checks whether data obtained by inverting a predetermined bit contained in the entry data where the bit error is detected is normal entry data. The replacement module replaces the entry data where the bit error is detected with the normal entry data.

Claims

1. A storage device comprising:

an error detector configured to detect a bit error in entry data related to conversion to a physical address corresponding to a logical address, based on an error-detecting code assigned to the entry data;

a check module configured to check that data obtained by inverting a bit contained in the entry data where the bit error is detected is normal entry data; and

a replacement module configured to replace the entry data where the bit error is detected with the normal entry data.

2. The storage device of claim 1, wherein

the check module is configured to sequentially invert bits contained in the entry data where the bit error is detected, and

when inversion of one of the bits results in data determined to be normal entry data, the replacement module is configured to replace the entry data where the bit error is detected with the normal entry data.

3. The storage device of claim 1, wherein the error-detecting code is a parity bit.

4. The storage device of claim 1, wherein, when the data obtained by inverting the bit contained in the entry data where the bit error is detected is entry data indicating a physical address of a range, the check module is configured to determine that the data is normal entry data.

5. The storage device of claim 1, further comprising an address management module configured to manage whether a physical address is active or inactive, wherein

when a physical address indicated by the data obtained by inverting the bit contained in the entry data where the bit error is detected is managed as an active physical address, the check module is configured to determine that the data is normal entry data.

6. The storage device of claim 2, further comprising an address management module configured to manage whether a physical address is active or inactive, wherein

when a physical address indicated by the data obtained by inverting the bit contained in the entry data where the bit error is detected is managed as an active physical address, the check module is configured to determine that the data is normal entry data.

7. The storage device of claim 1, wherein

a memory area is configured to store a logical address corresponding to a physical address, wherein the memory area is specified by the physical address, and

when a logical address read from a memory area specified by a physical address indicated by the data obtained by inverting the bit contained in the entry data where the bit error is detected matches a logical address related to the entry data where the bit error is detected, the check module is configured to determine that the data is normal entry data.

8. An electronic device comprising a storage device that comprises:

an error detector configured to detect a bit error in entry data related to conversion to a physical address corresponding to a logical address, based on an error-detecting code assigned to the entry data;

a check module configured to check that data obtained by inverting a bit contained in the entry data where the bit error is detected is normal entry data; and

a replacement module configured to replace the entry data where the bit error is detected with the normal entry data.

9. The electronic device of claim 8, wherein

the check module is configured to sequentially invert bits contained in the entry data where the bit error is detected, and

when inversion of one of the bits results in data determined to be normal entry data, the replacement module is configured to replace the entry data where the bit error is detected with the normal entry data.

10. The electronic device of claim 8, wherein the error-detecting code is a parity bit.

11. The electronic device of claim 8, wherein, when the data obtained by inverting the bit contained in the entry data where the bit error is detected is entry data indicating a physical address of a range, the check module is configured to determine that the data is normal entry data.

12. The electronic device of claim 8, further comprising an address management module configured to manage whether a physical address is active or inactive, wherein

when a physical address indicated by the data obtained by inverting the bit contained in the entry data where the bit error is detected is managed as an active physical address, the check module is configured to determine that the data is normal entry data.

13. The electronic device of claim 9, further comprising an address management module configured to manage whether a physical address is active or inactive, wherein

when a physical address indicated by the data obtained by inverting the bit contained in the entry data where the bit error is detected is managed as an active physical address, the check module is configured to determine that the data is normal entry data.

14. The electronic device of claim 8, wherein

a memory area is configured to store a logical address corresponding to a physical address, wherein the memory area is specified by the physical address, and

when a logical address read from a memory area specified by a physical address indicated by the data obtained by inverting the bit contained in the entry data where the bit error is detected matches a logical address related to the entry data where the bit error is detected, the check module is configured to determine that the data is normal entry data.

15. A method for correcting data error in a storage device configured to store data, the data error correction method comprising:

detecting a bit error that occurs in entry data related to conversion to a physical address corresponding to a logical address, based on an error-detecting code assigned to the entry data;

checking that data obtained by inverting a bit contained in the entry data where the bit error is detected is normal entry data; and

replacing the entry data where the bit error is detected with the normal entry data.

16. The data error correction method of claim 15, wherein

checking comprises sequentially inverting bits contained in the entry data where the bit error is detected, and

replacing the entry data where the bit error is detected with the normal entry data is performed when inversion of one of the bits provides data determined to be normal entry data.

17. The data error correction method of claim 15, wherein the error-detecting code is a parity bit.

18. The data error correction method of claim 15, wherein, checking that the data is normal entry data is performed when the data obtained by inverting the bit contained in the entry data where the bit error is detected is entry data indicating a physical address of a range.

19. The data error correction method of claim 15, further comprising managing whether a physical address is active or inactive, wherein

checking that the data is normal entry data is performed when a physical address indicated by the data obtained by inverting the bit contained in the entry data where the bit error is detected is managed as an active physical address.

20. The data error correction method of claim 15, wherein

a logical address corresponding to a physical address is stored in a memory area specified by the physical address, and wherein

checking that the data is normal entry data is performed when a logical address read from a memory area specified by a physical address indicated by the data obtained by inverting the bit contained in the entry data where the bit error is detected matches a logical address related to the entry data where the bit error is detected.