POWER-INSULATED-GATE FIELD-EFFECT TRANSISTOR

• US 20120068183A1
• Filed: 09/19/2011
• Published: 03/22/2012
• Est. Priority Date: 09/22/2010
• Status: Active Grant

• Current Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Original Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Inventors: Takemura, Yasuhiko
• Granted Patent: US 8,994,003 B2
• Time in Patent Office: Days
• US Class Current: 257/60
• CPC Class Codes: H01L 29/7869 having a semiconductor body comprising an oxide semiconductor material, e.g. zinc oxide, copper aluminium oxide, cadmium stannate

Abstract

To provide a power MISFET using oxide semiconductor. A gate electrode, a source electrode, and a drain electrode are formed so as to interpose a semiconductor layer therebetween, and a region of the semiconductor layer where the gate electrode and the drain electrode do not overlap with each other is provided between the gate electrode and the drain electrode. The length of the region is from 0.5 μm to 5 μm. In such a power MISFET, a power source of 100 V or higher and a load are connected in series between the drain electrode and the source electrode, and a control signal is input to the gate electrode.

Claims

1. A power insulated gate field effect transistor comprising:

a gate electrode;

an oxide semiconductor layer over the gate electrode, the oxide semiconductor layer comprises a first portion and a second portion;

one of a source and a drain electrode on the second portion; and

the other of the source and the drain electrode on the first portion,

wherein;

a thickness of the first portion is larger than a thickness of the second portion; and

the thickness of the first portion is from 0.5 μ

m to 5 μ

m.

2. The power insulated gate field effect transistor according to claim 1, wherein the oxide semiconductor layer is interposed between the gate electrode and a back gate electrode.

3. The power insulated gate field effect transistor according to claim 1, wherein a concentration of carriers originated from donor or acceptor in the oxide semiconductor layer is 1×

10¹² cm<sup>−

3</sup> or lower.

4. The power insulated gate field effect transistor according to claim 1, wherein a concentration of hydrogen in the oxide semiconductor layer is 1×

10¹⁸ cm<sup>−

3</sup> or lower.

5. The power insulated gate field effect transistor according to claim 1, wherein each one of a work function of a portion of the one of the source and the drain electrode which is in contact with the oxide semiconductor layer and a work function of a portion of the other of the source and the drain electrode which is in contact with the oxide semiconductor layer is smaller than a sum of an electron affinity of the oxide semiconductor layer and 0.3 eV.

6. The power insulated gate field effect transistor according to claim 1, wherein a work function of the one of the source and the drain electrode is higher than a work function of the other of the source and the drain electrode.

7. The power insulated gate field effect transistor according to claim 1,

wherein a junction between the oxide semiconductor layer and the one of the source and the drain electrode is an ohmic contact, and

wherein a junction between the oxide semiconductor layer and the other of the source and the drain electrode is an ohmic contact.

8. The power insulated gate field effect transistor according to claim 1, wherein a work function of a portion of the gate electrode which is in contact with a gate insulating film is larger than a sum of an electron affinity of the oxide semiconductor layer and 0.6 eV.

9. The power insulated gate field effect transistor according to claim 1, wherein the thickness of the first portion is from 10 nm to 100 nm.

10. The power insulated gate field effect transistor according to claim 1, wherein a width of the other of the source and the drain electrode is from 2 μ

m to 10 μ

m.

11. The power insulated gate field effect transistor according to claim 2, wherein an interval between the back gate electrode and the other of the source and the drain electrode is from 0.3 μ

m to 2 μ

m.

12. The power insulated gate field effect transistor according to claim 1, wherein an on-state resistance of the power insulated gate field effect transistor is 0.8Ω

or lower at a withstand voltage of 300 V.

13. The power insulated gate field effect transistor according to claim 1 further comprising a power of 100 V or higher and a load electrically connected in series between the one of the source and the drain electrode and the other of the source and the drain electrode.

14. The power insulated gate field effect transistor according to claim 1,

wherein the one of the source and the drain electrode is a source electrode, and

wherein the other of the source and the drain electrode is a drain electrode.

15. A power insulated gate field effect transistor comprising:

a gate electrode;

an oxide semiconductor layer over the gate electrode;

one of a source and a drain electrode on the oxide semiconductor layer; and

the other of the source and the drain electrode on the oxide semiconductor layer,

wherein;

the one of the source and the drain electrode overlaps with a part of the gate electrode;

the other of the source and the drain electrode does note overlap with the gate electrode;

the oxide semiconductor layer includes a region between the gate electrode and the other of the source and the drain electrode, the region does not overlap with the gate electrode and the other of the source and the drain electrode; and

a length of the region is from 0.5 μ

m to 5 μ

m.

16. The power insulated gate field effect transistor according to claim 15, wherein the oxide semiconductor layer is interposed between the gate electrode and a back gate electrode.

17. The power insulated gate field effect transistor according to claim 15, wherein a concentration of carriers originated from donor or acceptor in the oxide semiconductor layer is 1×

10¹² cm<sup>−

3</sup> or lower.

18. The power insulated gate field effect transistor according to claim 15, wherein a concentration of hydrogen in the oxide semiconductor layer is 1×

10¹⁸ cm<sup>−

3</sup> or lower.

19. The power insulated gate field effect transistor according to claim 15, wherein each one of a work function of a portion of the one of the source and the drain electrode which is in contact with the oxide semiconductor layer and a work function of a portion of the other of the source and the drain electrode which is in contact with the oxide semiconductor layer is smaller than a sum of an electron affinity of the oxide semiconductor layer and 0.3 eV.

20. The power insulated gate field effect transistor according to claim 15, wherein a work function of the one of the source and the drain electrode is higher than a work function of the other of the source and the drain electrode.

21. The power insulated gate field effect transistor according to claim 15,

wherein a junction between the oxide semiconductor layer and the one of the source and the drain electrode is an ohmic contact, and

wherein a junction between the oxide semiconductor layer and the other of the source and the drain electrode is an ohmic contact.

22. The power insulated gate field effect transistor according to claim 15, wherein a work function of a portion of the gate electrode which is in contact with a gate insulating film is larger than a sum of an electron affinity of the oxide semiconductor layer and 0.6 eV.

23. The power insulated gate field effect transistor according to claim 15, wherein a thickness of the oxide semiconductor layer is from 10 nm to 100 nm.

24. The power insulated gate field effect transistor according to claim 15, wherein an on-state resistance of the power insulated gate field effect transistor is 0.8Ω

or lower at a withstand voltage of 300 V.

25. The power insulated gate field effect transistor according to claim 15 further comprising a power of 100 V or higher and a load electrically connected in series between the one of the source and the drain electrode and the other of the source and the drain electrode.

26. The power insulated gate field effect transistor according to claim 15,

wherein the one of the source and the drain electrode is a source electrode, and

wherein the other of the source and the drain electrode is a drain electrode.

27. A power insulated gate field effect transistor comprising:

a gate electrode;

an oxide semiconductor layer over the gate electrode, the oxide semiconductor layer comprises a first portion and a second portion; and

one of a source and a drain electrode on the first portion,

wherein;

the second portion includes a channel region;

a thickness of the first portion is larger than a thickness of the second portion; and

the thickness of the first portion is from 0.5 μ

m to 5 μ

m.

28. The power insulated gate field effect transistor according to claim 27, wherein the oxide semiconductor layer is interposed between the gate electrode and a back gate electrode.

29. The power insulated gate field effect transistor according to claim 27, wherein a concentration of carriers originated from donor or acceptor in the oxide semiconductor layer is 1×

10¹² cm<sup>−

3</sup> or lower.

30. The power insulated gate field effect transistor according to claim 27, wherein a concentration of hydrogen in the oxide semiconductor layer is 1×

10¹⁸ cm<sup>−

3</sup> or lower.

31. The power insulated gate field effect transistor according to claim 27, wherein each one of a work function of a portion of the one of the source and the drain electrode which is in contact with the oxide semiconductor layer and a work function of a portion of the other of the source and the drain electrode which is in contact with the oxide semiconductor layer is smaller than a sum of an electron affinity of the oxide semiconductor layer and 0.3 eV.

32. The power insulated gate field effect transistor according to claim 27, wherein a work function of the other of the source and the drain electrode is higher than a work function of the one of the source and the drain electrode.

33. The power insulated gate field effect transistor according to claim 27,

wherein a junction between the oxide semiconductor layer and the one of the source and the drain electrode is an ohmic contact, and

wherein a junction between the oxide semiconductor layer and the other of the source and the drain electrode is an ohmic contact.

34. The power insulated gate field effect transistor according to claim 27, wherein a work function of a portion of the gate electrode which is in contact with a gate insulating film is larger than a sum of an electron affinity of the oxide semiconductor layer and 0.6 eV.

35. The power insulated gate field effect transistor according to claim 27, wherein the thickness of the first portion is from 10 nm to 100 nm.

36. The power insulated gate field effect transistor according to claim 27, wherein a width of the one of the source and the drain electrode is from 2 μ

m to 10 μ

m.

37. The power insulated gate field effect transistor according to claim 28, wherein an interval between the back gate electrode and the one of the source and the drain electrode is from 0.3 μ

m to 2 μ

m.

38. The power insulated gate field effect transistor according to claim 27, wherein an on-state resistance of the power insulated gate field effect transistor is 0.8Ω

or lower at a withstand voltage of 300 V.

39. The power insulated gate field effect transistor according to claim 27 further comprising a power of 100 V or higher and a load electrically connected in series between the one of the source and the drain electrode and the other of the source and the drain electrode.

40. The power insulated gate field effect transistor according to claim 27, wherein the one of the source and the drain electrode is a drain electrode.