Massively Parallel Interconnect Fabric for Complex Semiconductor Devices

• US 20120068229A1
• Filed: 11/27/2011
• Published: 03/22/2012
• Est. Priority Date: 05/06/2009
• Status: Active Grant

• Current Assignee: Farhang Yazdani, Majid Bemanian
• Original Assignee: Farhang Yazdani, Majid Bemanian
• Inventors: Bemanian, Majid, Yazdani, Farhang
• Granted Patent: US 9,035,443 B2
• Time in Patent Office: Days
• US Class Current: 257/209
• CPC Class Codes: G11C 5/04 Supports for storage elements , e.g. memory modules; Mounting or fixing of storage elements on such supports
• CPC Class Codes: H01L 2223/6677 for antenna, e.g. antenna included within housing of semiconductor device
• CPC Class Codes: H01L 2224/0401 Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
• CPC Class Codes: H01L 2224/0612 Layout
• CPC Class Codes: H01L 2224/06135 Covering only the peripheral area of the surface to be connected, i.e. peripheral arrangements
• CPC Class Codes: H01L 2224/0615 Mirror array, i.e. array having only a reflection symmetry, i.e. bilateral symmetry
• CPC Class Codes: H01L 2224/1403 Bump connectors having different sizes, e.g. different diameters, heights or widths
• CPC Class Codes: H01L 2224/16145 the bodies being stacked
• CPC Class Codes: H01L 2224/16225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/48145 the bodies being stacked
• CPC Class Codes: H01L 2225/06513 Bump or bump-like direct electrical connections between devices, e.g. flip-chip connection, solder bumps
• CPC Class Codes: H01L 2225/06517 Bump or bump-like direct electrical connections from device to substrate
• CPC Class Codes: H01L 2225/0652 Bump or bump-like direct electrical connections from substrate to substrate
• CPC Class Codes: H01L 2225/06527 Special adaptation of electrical connections, e.g. rewiring, engineering changes, pressure contacts, layout
• CPC Class Codes: H01L 2225/06541 Conductive via connections through the device, e.g. vertical interconnects, through silicon via [TSV]
• CPC Class Codes: H01L 2225/06548 Conductive via connections through the substrate, container, or encapsulation
• CPC Class Codes: H01L 2225/06572 Auxiliary carrier between devices, the carrier having an electrical connection structure
• CPC Class Codes: H01L 2225/06589 Thermal management, e.g. cooling
• CPC Class Codes: H01L 23/3121 a substrate forming part of the encapsulation
• CPC Class Codes: H01L 23/525 with adaptable interconnections
• CPC Class Codes: H01L 25/0652 : the devices being arranged next and on each other, i.e. mixed assemblies
• CPC Class Codes: H01L 25/0655 : the devices being arranged next to each other
• CPC Class Codes: H01L 25/0657 : Stacked arrangements of devices
• CPC Class Codes: H01L 25/105 : the devices being of a type provided for in group H01L27/00
• CPC Class Codes: H01L 25/18 : the devices being of types provided for in two or more different subgroups of the same main group of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N
• CPC Class Codes: H01L 2924/00 : Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00012 : Relevant to the scope of the group, the symbol of which is combined with the symbol of this group
• CPC Class Codes: H01L 2924/01019 : Potassium [K]
• CPC Class Codes: H01L 2924/01087 : Francium [Fr]
• CPC Class Codes: H01L 2924/1433 : Application-specific integrated circuit [ASIC]
• CPC Class Codes: H01L 2924/15151 : the die mounting substrate comprising an aperture, e.g. for underfilling, outgassing, window type wire connections
• CPC Class Codes: H01L 2924/15153 : the die mounting substrate comprising a recess for hosting the device
• CPC Class Codes: H01L 2924/15311 : being a ball array, e.g. BGA
• CPC Class Codes: H01L 2924/19041 : being a capacitor
• CPC Class Codes: H01L 2924/19042 : being an inductor
• CPC Class Codes: H01L 2924/19043 : being a resistor
• CPC Class Codes: H01L 2924/19101 : of discrete passive components
• CPC Class Codes: H01L 2924/30107 : Inductance

Abstract

An embodiment of this invention uses a massive parallel interconnect fabric (MPIF) at the flipped interface of a core die substrate (having the core logic blocks) and a context die (used for in circuit programming/context/customization of the core die substrate), to produce ASIC-like density and FPGA-like flexibility/programmability, while reducing the time and cost for development and going from prototyping to production, reducing cost per die, reducing or eliminating NRE, and increasing performance. Other embodiments of this invention enable debugging complex SoC through large contact points provided through the MPIF, provide for multi-platform functionality, and enable incorporating FGPA core in ASIC platform through the MPIF. Various examples are also given for different implementations.

Claims

1. A semiconductor system, said system comprising:

a programmable semiconductor die substrate;

a context die substrate; and

an interconnect switch fabric;

said programmable semiconductor die substrate comprises first multiple logic blocks;

said context die substrate is flipped on said programmable semiconductor die substrate;

said interconnect switch fabric interconnects among some or all of a hybrid programmable logic array'"'"'s logical blocks;

said first multiple logic blocks of said programmable semiconductor die substrate are electrically connected;

said context die substrate customizes an application for said first multiple logic blocks via electrical connection through said interconnect switch fabric.

2. The semiconductor system as recited in claim 1, wherein a first of said first multiple logic blocks of said programmable semiconductor die substrate is connected to itself, at transistor or gate level, with wirebondless and bumpless electrical connections, via said context die substrate, through pads of said interconnect switch fabric.

3. The semiconductor system as recited in claim 1, wherein said system comprises a core stack.

4. The semiconductor system as recited in claim 1, wherein said system comprises a base stack.

5. The semiconductor system as recited in claim 1, wherein said system comprises a redistribution or metal layer.

6. The semiconductor system as recited in claim 1, wherein a programming is done through said interconnect switch fabric residing on said context die substrate.

7. The semiconductor system as recited in claim 1, wherein a programming is done through a programming interface in said context die substrate.

8. The semiconductor system as recited in claim 1, wherein said interconnect switch fabric comprises pads, metal layers, vias, MUXes, switches, and redistribution layers.

9. The semiconductor system as recited in claim 1, wherein said programmable semiconductor die substrate is flipped into a package substrate, to provide electrical connection between said programmable semiconductor die substrate and said package substrate.

10. The semiconductor system as recited in claim 1, wherein said system comprises more than one redistribution or metal layers.

11. The semiconductor system as recited in claim 1, wherein said system comprises separated fabric.

12. The semiconductor system as recited in claim 1, wherein said system comprises separated programming memory.

13. The semiconductor system as recited in claim 1, wherein said system comprises separated logic.

14. The semiconductor system as recited in claim 1, further comprising a customizable interconnect switch.

15. The semiconductor system as recited in claim 14, wherein said customizable interconnect switch is a MUX.

16. The semiconductor system as recited in claim 1, further comprising a field programmable interconnect switch.

17. The semiconductor system as recited in claim 16, wherein said field programmable interconnect switch is based on direct-bonding.

18. The semiconductor system as recited in claim 1, wherein each of said first multiple logic blocks comprises one or more logic elements.

19. The semiconductor system as recited in claim 18, wherein said one or more logic elements comprise combinational logic or lookup table.

20. The semiconductor system as recited in claim 18, wherein said one or more logic elements comprise a clocked flip-flop.

21. The semiconductor system as recited in claim 1, wherein said system comprises a hardened redistribution layer.