TRANSITION FROM A CHIP TO A WAVEGUIDE PORT
First Claim
1. A transition from a first planar structure (1, 1′
- , 62) in the form of a chip to a waveguide port (47, 47′
, 77), the first planar structure (1, 1′
, 62) having a first main side (3, 3′
, 66) and a second main side (4, 4′
, 67), where the first main side (3, 3′
, 66) comprises at least one input port (35, 36, 37, 38, 39), arranged to receive an input signal, at least one output port (44, 45;
72), arranged to output an output signal, and at least one electrical functionality, characterized in that one port (44, 72) of said ports (44, 45;
72;
35, 36, 37, 38, 39) is electrically connected to an electrically conducting probe (48, 48′
, 73) that is arranged to extend from said one port (44, 72) and at least partly over the waveguide port (47, 47′
, 77) such that a signal may be transferred between said one port (44, 72) and the waveguide port (47, 47′
, 77).
8 Assignments
0 Petitions
Accused Products
Abstract
The present invention relates to a transition from a chip to a waveguide port (47, 47′, 11), the chip (1, 1′, 62) having a first main side (3, 3′, 66) and a second main side (4, 4′, 67), where the first main side (3, 3′, 66) comprises at least one input port (35, 36, 37, 38, 39), arranged to receive an input signal, at least one output port (44, 45; 72), arranged to output an output signal, and at least one electrical functionality. One port (44, 72) of said ports (44, 45; 72; 35, 36, 37, 38, 39) is electrically connected to an electrically conducting probe (48, 48′, 73) that is arranged to extend from said one port (44, 72) and at least partly over the waveguide port (47, 47′, 77) such that a signal may be transferred between said one port (44, 72) and the waveguide port (47, 47′, 77). The present invention also relates to a corresponding package.
40 Citations
19 Claims
-
1. A transition from a first planar structure (1, 1′
- , 62) in the form of a chip to a waveguide port (47, 47′
, 77), the first planar structure (1, 1′
, 62) having a first main side (3, 3′
, 66) and a second main side (4, 4′
, 67), where the first main side (3, 3′
, 66) comprises at least one input port (35, 36, 37, 38, 39), arranged to receive an input signal, at least one output port (44, 45;
72), arranged to output an output signal, and at least one electrical functionality, characterized in that one port (44, 72) of said ports (44, 45;
72;
35, 36, 37, 38, 39) is electrically connected to an electrically conducting probe (48, 48′
, 73) that is arranged to extend from said one port (44, 72) and at least partly over the waveguide port (47, 47′
, 77) such that a signal may be transferred between said one port (44, 72) and the waveguide port (47, 47′
, 77). - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11)
- , 62) in the form of a chip to a waveguide port (47, 47′
-
12. A package comprising a chip (1, 1′
- , 62) having a plurality of electrical functions, and where bond wires (46) connect chip connections (35, 36, 37, 38, 39, 40, 41, 42, 43, 45) to corresponding package connections (22, 23, 24, 25, 26, 7, 8, 20, 19, 9) comprised in a base structure (5), where the base structure (5) and the chip (1, 1′
) at least partly are comprised inside a moulding (32), forming said package with said package connections (22, 23, 24, 25, 26, 7, 8, 20, 19, 9) accessible, characterized in that the package comprises a transition from the chip (1, 1′
, 62) to a waveguide port (47, 47′
, 77), the chip (1, 1′
, 62) having a first main side (3, 3′
, 66) and a second main side (4, 4′
, 67), where the first main side (3, 3′
, 66) comprises at least one input port (35, 36, 37, 38, 39), arranged to receive an input signal, at least one output port (44, 45;
72), arranged to output an output signal, and at least one electrical functionality, where one port (44, 72) of said ports (44, 45;
72;
35, 36, 37, 38, 39) is electrically connected to an electrically conducting probe (48, 48′
, 73) that is arranged to extend from said one port (44, 72) and at least partly over the waveguide port (47, 47′
, 77) such that a signal may be transferred between said one port (44, 72) and the waveguide port (47, 47′
, 77). - View Dependent Claims (13, 14, 15, 16, 17, 18, 19)
- , 62) having a plurality of electrical functions, and where bond wires (46) connect chip connections (35, 36, 37, 38, 39, 40, 41, 42, 43, 45) to corresponding package connections (22, 23, 24, 25, 26, 7, 8, 20, 19, 9) comprised in a base structure (5), where the base structure (5) and the chip (1, 1′
Specification