METHOD FOR PROCESSING SEMICONDUCTOR STRUCTURE AND DEVICE BASED ON THE SAME

• US 20120068347A1
• Filed: 09/20/2010
• Published: 03/22/2012
• Est. Priority Date: 09/20/2010
• Status: Active Grant

• Current Assignee: Kabushiki Kaisha Toshiba (Toshiba Corporation)
• Original Assignee: Toshiba America Electronic Components Incorporated (Toshiba Corporation)
• Inventors: Isobayashi, Atsunobu, Ishikawa, Masao
• Granted Patent: US 8,138,097 B1
• Time in Patent Office: Days
• US Class Current: 257/773
• CPC Class Codes: H01L 21/0332 characterised by their composition, e.g. multilayer masks, materials
• CPC Class Codes: H01L 21/0337 characterised by the process involved to create the mask, e.g. lift-off masks, sidewalls, or to modify the mask, e.g. pre-treatment, post-treatment
• CPC Class Codes: H01L 21/31144 using masks

Abstract

Methods for fabricating a device and related device structures are provided herein. According to one embodiment, a method for fabricating a device includes the acts of producing a substrate; forming a structure on the substrate having a lower dielectric layer, a metal layer, an upper dielectric layer, a planarizing layer, and a layer of photoresist material; developing the photoresist material according to a mask pattern; etching the planarizing layer and the upper dielectric layer according to the mask pattern; removing the photoresist material and the planarizing layer upon etching of the planarizing layer and the upper dielectric layer; applying a selective metal growth or metal/organic film to respective exposed portions of the metal layer following etching of the upper dielectric layer, thereby obtaining an inverted mask pattern; and etching at least the metal layer and the lower dielectric layer according to the inverted mask pattern.

Claims

1. A method for fabricating a device, comprising:

forming a structure on a substrate, the structure having a lower dielectric layer on the substrate, a metal layer on the lower dielectric layer, an upper dielectric layer on the metal layer, a planarizing layer on the upper dielectric layer, and a layer of photoresist material on the planarizing layer;

developing the photoresist material according to a mask pattern;

etching the planarizing layer and the upper dielectric layer according to the mask pattern;

removing the photoresist material and the planarizing layer upon etching of the planarizing layer and the upper dielectric layer;

applying a selective metal growth to respective exposed portions of the metal layer following etching of the upper dielectric layer, thereby obtaining an inverted mask pattern composed of the selective metal growth; and

etching at least the metal layer and the lower dielectric layer according to the inverted mask pattern.

2. The method of claim 1, further comprising removing the upper dielectric layer prior to etching the metal layer and the lower dielectric layer.

3. The method of claim 1, wherein the applying comprises applying the selective metal growth via at least one of electroless plating, epitaxial growth, chemical vapor deposition (CVD), physical vapor deposition (PVD), or atomic layer deposition (ALD).

4. The method of claim 1, wherein:

the upper dielectric layer has a thickness between approximately 10 nm and approximately 100 nm; and

the metal layer has a thickness between approximately 5 nm and approximately 20 nm.

5. The method of claim 1, wherein the applying comprises applying selective metal growth composed of at least one element selected from the group consisting of Co, Ni, Cu, Fe, Ru, Rh, Pd, Ag, Os, Ir, Sn, Pb, Pt, and Au.

6. The method of claim 1, wherein the applying comprises applying selective metal growth comprising at least one primary metal and at least one co-deposit metal.

7. The method of claim 6, wherein:

the at least one primary metal is composed of at least one element selected from the group consisting of Co, Ni, Cu, Fe, Ru, Rh, Pd, Ag, Os, Ir, Sn, Pb, Pt, and Au; and

the at least one co-deposit metal comprises is composed of at least one element selected from the group consisting of V, Cr, Mn, Mo, Tc, W, Rc, In, Ti, Zn, Si, Ge, and B.

8. The method of claim 1, further comprising:

removing the selective metal growth and the metal layer following etching of the metal layer and the lower dielectric layer;

metalizing one or more portions of the lower dielectric layer that are removed as a result of the etching of the lower dielectric layer; and

forming a cap layer on the lower dielectric layer upon completion of the metalizing.

9. A method for fabricating a device, comprising:

forming a structure on a substrate, the structure having a lower dielectric layer on the substrate, a metal layer on the lower dielectric layer, an upper dielectric layer on the metal layer, a planarizing layer on the upper dielectric layer, and a layer of photoresist material on the planarizing layer;

developing the photoresist material according to a mask pattern;

etching the planarizing layer and the upper dielectric layer according to the mask pattern;

removing the photoresist material and the planarizing layer upon etching of the planarizing layer and the upper dielectric layer;

depositing a metal or organic film on the upper dielectric layer and respective exposed portions of the metal layer following etching of the upper dielectric layer;

removing respective portions of the metal or organic film that are located on one or more portions of the upper dielectric layer, thereby obtaining an inverted mask pattern composed of the metal or organic film; and

etching at least the metal layer and the lower dielectric layer according to the inverted mask pattern.

10. The method of claim 9, further comprising removing the upper dielectric layer prior to etching the metal layer and the lower dielectric layer.

11. The method of claim 9, wherein the depositing comprises depositing the metal or organic film via at least one of electroless plating, epitaxial growth, chemical vapor deposition (CVD), physical vapor deposition (PVD), or atomic layer deposition (ALD).

12. The method of claim 9, wherein:

the upper dielectric layer has a thickness between approximately 10 nm and approximately 100 nm; and

the metal layer has a thickness between approximately 5 nm and approximately 20 nm.

13. The method of claim 9, wherein the metal or organic film is a metal film composed of at least one of a material selected from the group consisting of W, Cu, Ti, TiN, Ru, Ta, TaN, Co, Ni, and Si;

carbon combined with a material selected from the group consisting of W, Cu, Ti, TiN, Ru, Ta, TaN, Co, Ni, and Si;

or an alloy combined with a material selected from the group consisting of W, Cu, Ti, TiN, Ru, Ta, TaN, Co, Ni, and Si.

14. The method of claim 9, wherein the metal or organic film is an organic film composed of amorphous carbon.

15. The method of claim 9, wherein the metal or organic film has a thickness between approximately 10 nm and approximately 300 nm.

16. The method of claim 9, wherein the depositing comprises:

depositing an initial layer of metal or organic film on the upper dielectric layer and respective exposed portions of the metal layer following etching of the upper dielectric layer; and

depositing a primary layer of metal or organic film on the initial layer of metal or organic film.

17. The method of claim 16, wherein the initial layer of metal or organic film is composed of at least one of Ti, TiN, Ta, or TaN.

18. The method of claim 16, wherein the initial layer of metal or organic film has a thickness between approximately 1 nm and approximately 10 nm.

19. The method of claim 9, further comprising:

removing the metal or organic film and the metal layer following etching of the metal layer and the lower dielectric layer;

metalizing one or more portions of the lower dielectric layer that are removed as a result of the etching of the lower dielectric layer; and

forming a cap layer on the lower dielectric layer upon completion of the metalizing.

20. A product, comprising:

a substrate; and

a laminated structure formed on the substrate, the laminated structure comprising;

a lower dielectric layer formed in the semiconductor region;

a metal layer deposited onto the lower dielectric layer;

an upper dielectric layer formed onto the metal layer;

a planarizing layer formed onto the upper dielectric layer; and

photoresist material deposited onto the planarizing layer;

wherein the photoresist material is configured to be selectively removed according to a mask pattern, the planarizing layer and the upper dielectric layer are configured for etching according to the mask pattern, and one or more regions of the metal layer are configured to receive at least one material selected from the group consisting of selective metal growth, metal film, and organic film, whereby material received at the one or more regions of the metal layer form an inverted mask pattern for etching of at least the metal layer and the lower dielectric layer.