INTEGRATED CIRCUIT WITH INTRA-CHIP CLOCK INTERFACE AND METHODS FOR USE THEREWITH

• US 20120069537A1
• Filed: 11/29/2011
• Published: 03/22/2012
• Est. Priority Date: 06/21/2006
• Status: Active Grant

• Current Assignee: Avago Technologies International Sales Pte Limited (Broadcom, Inc.)
• Original Assignee: Broadcom Corporation (Broadcom, Inc.)
• Inventors: Rofougaran, Ahmadreza (Reza)
• Granted Patent: US 8,520,400 B2
• Time in Patent Office: Days
• US Class Current: 361/764
• CPC Class Codes: H01L 2223/6627 Waveguides, e.g. microstrip line, strip line, coplanar line
• CPC Class Codes: H01L 2223/6677 for antenna, e.g. antenna included within housing of semiconductor device antennas per se H01Q
• CPC Class Codes: H01L 2224/05554 being square
• CPC Class Codes: H01L 2224/05599 Material
• CPC Class Codes: H01L 2224/45099 Material
• CPC Class Codes: H01L 2224/48091 Arched
• CPC Class Codes: H01L 2224/49175 Parallel arrangements
• CPC Class Codes: H01L 2224/85399 Material
• CPC Class Codes: H01L 2225/06527 Special adaptation of electrical connections, e.g. rewiring, engineering changes, pressure contacts, layout
• CPC Class Codes: H01L 23/66 High-frequency adaptations
• CPC Class Codes: H01L 24/06 of a plurality of bonding areas
• CPC Class Codes: H01L 24/48 of an individual wire connector
• CPC Class Codes: H01L 24/49 of a plurality of wire connectors
• CPC Class Codes: H01L 25/0655 the devices being arranged next to each other
• CPC Class Codes: H01L 25/0657 Stacked arrangements of devices
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00014 the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/01005 Boron [B]
• CPC Class Codes: H01L 2924/01006 Carbon [C]
• CPC Class Codes: H01L 2924/01014 Silicon [Si]
• CPC Class Codes: H01L 2924/01015 : Phosphorus [P]
• CPC Class Codes: H01L 2924/01023 : Vanadium [V]
• CPC Class Codes: H01L 2924/01027 : Cobalt [Co]
• CPC Class Codes: H01L 2924/01031 : Gallium [Ga]
• CPC Class Codes: H01L 2924/01032 : Germanium [Ge]
• CPC Class Codes: H01L 2924/01033 : Arsenic [As]
• CPC Class Codes: H01L 2924/0106 : Neodymium [Nd]
• CPC Class Codes: H01L 2924/01061 : Promethium [Pm]
• CPC Class Codes: H01L 2924/01083 : Bismuth [Bi]
• CPC Class Codes: H01L 2924/1305 : Bipolar Junction Transistor [BJT]
• CPC Class Codes: H01L 2924/13091 : Metal-Oxide-Semiconductor Field-Effect Transistor [MOSFET]
• CPC Class Codes: H01L 2924/14 : Integrated circuits
• CPC Class Codes: H01L 2924/1433 : Application-specific integrated circuit [ASIC]
• CPC Class Codes: H01L 2924/1461 : MEMS
• CPC Class Codes: H01L 2924/19033 : being a coplanar line type
• CPC Class Codes: H01L 2924/19041 : being a capacitor
• CPC Class Codes: H01L 2924/19042 : being an inductor
• CPC Class Codes: H01L 2924/19043 : being a resistor
• CPC Class Codes: H01L 2924/30105 : Capacitance
• CPC Class Codes: H01L 2924/30107 : Inductance
• CPC Class Codes: H01L 2924/3011 : Impedance
• CPC Class Codes: H01L 2924/30111 : matching
• CPC Class Codes: H01Q 1/2283 : mounted in or on the surface of a semiconductor substrate as a chip-type antenna or integrated with other components into an IC package
• CPC Class Codes: H01Q 1/38 : formed by a conductive layer on an insulating support patch antennas H01Q9/0407; microstrip dipole antennas H01Q9/065; microstrip slot antennas H01Q13/106; transmission line microstrip antennas H01Q13/206; manufacturing reflecting surfaces using insulating material for supporting the reflecting surface H01Q15/142
• CPC Class Codes: H01Q 23/00 : Antennas with active circuits or circuit elements integrated within them or attached to them
• CPC Class Codes: H01Q 9/065 : Microstrip dipole antennas patch antenna H01Q9/0407

Abstract

An integrated circuit includes a substrate. A first integrated circuit die includes a first circuit and a first intra-chip clock interface that transmits a first clock signal via the substrate. A second integrated circuit die includes a second circuit that operates based on the first clock signal and a second intra-chip clock interface that recovers the first clock signal from the substrate.

Claims

1. An integrated circuit comprising:

a substrate;

a first integrated circuit die coupled to the substrate, the first integrated circuit die including a first intra-chip clock interface coupled to the substrate that transmits a first clock signal;

a second integrated circuit die coupled to the substrate, the second integrated circuit die including;

a circuit that operates based on the first clock signal;

a second intra-chip clock interface coupled to the substrate that recovers the first clock signal;

wherein the substrate includes wave guide for coupling the first clock signal from the first intra-chip clock interface to the second intra-chip clock interface as a radio frequency signal.

2. The integrated circuit of claim 1 wherein the first clock signal is at a millimeter wave frequency.

3. The integrated circuit of claim 1 wherein the first intra-chip clock interface further transmits a second clock signal;

wherein the second intra-chip clock interface recovers the second clock signal; and

wherein the circuit further operates based on the second clock signal.

4. The integrated circuit of claim 1 wherein the second intra-chip clock interface includes a clock generation module that generates a second clock signal based on the first clock signal.

5. The integrated circuit of claim 1 wherein the second intra-chip clock interface includes a clock generation module that generates a plurality of second clock signals based on the first clock signal.

6. An integrated circuit comprising:

a substrate;

a first integrated circuit die coupled to the substrate, the first integrated circuit die including a first intra-chip clock interface coupled to the substrate that transmits a first clock signal;

a second integrated circuit die coupled to the substrate, the second integrated circuit die including;

a circuit that operates based on the first clock signal;

a second intra-chip clock interface coupled to the substrate that recovers the first clock signal;

wherein the substrate includes a magnetic path for inductively coupling the first clock signal from the first intra-chip clock interface to the second intra-chip clock interface.

7. The integrated circuit of claim 6 wherein the first clock signal is at a millimeter wave frequency.

8. The integrated circuit of claim 6 wherein the first intra-chip clock interface further transmits a second clock signal;

wherein the second intra-chip clock interface recovers the second clock signal; and

wherein the circuit operates based on the second clock signal.

9. The integrated circuit of claim 6 wherein the second intra-chip clock interface includes a clock generation module that generates a second clock signal based on the first clock signal.

10. The integrated circuit of claim 6 wherein the second intra-chip clock interface includes a clock generation module that generates a plurality of second clock signals based on the first clock signal.

11. A method comprising:

communicating a first clock signal having a millimeter wave frequency from a first integrated circuit die to a second integrated circuit via a substrate that supports the first integrated circuit die and the second integrated circuit die.

12. The method of claim 11 wherein the first clock signal is communicated electromagnetically via a waveguide in the substrate.

13. The method of claim 11 wherein the first clock signal is communicated inductively via a magnetic path in the substrate.