FERROELECTRIC MEMORY

• US 20120069623A1
• Filed: 09/12/2011
• Published: 03/22/2012
• Est. Priority Date: 09/17/2010
• Status: Active Grant

• Current Assignee: Kioxia Corporation
• Original Assignee: Kabushiki Kaisha Toshiba (Toshiba Corporation)
• Inventors: MIYAKAWA, Tadashi, Takashima, Daisaburo
• Granted Patent: US 8,619,455 B2
• Time in Patent Office: Days
• US Class Current: 365/145
• CPC Class Codes: G11C 11/22 using ferroelectric elements

Abstract

One embodiment provides a ferroelectric memory including: memory cells each including a ferroelectric memory; first and second bitlines configured to read out cell signals from the memory cells; a first circuit configured to fix, when the cell signal is read from the memory cell to the first bitline, a voltage of the second bitline to a first power-supply voltage, and then set the second bitline to a second power-supply voltage different from the first power-supply voltage; a second circuit configured to set, after the first circuit sets the second bitline to the second power-supply voltage, the second bitline to a reference voltage; and a third circuit configured to amplify a voltage difference between the first bitline to which the cell signal is read and the second bitline to which the reference voltage is set.

Claims

1. A ferroelectric memory comprising:

a plurality of memory cells, each of the memory cells including a ferroelectric memory;

first and second bitlines facing each other in parallel and configured to read cell signals from the memory cells;

a first circuit configured to

fix, when the cell signal is read from the memory cell to the first bitline, a voltage of the second bitline to a first power-supply voltage, and

then set the second bitline to a second power-supply voltage different from the first power-supply voltage;

a second circuit configured to set, after the first circuit sets the second bitline to the second power-supply voltage, the second bitline to a reference voltage; and

a third circuit configured to amplify a voltage difference between the first bitline to which the cell signal is read and the second bitline to which the reference voltage is set.

2. The ferroelectric memory of claim 1,

wherein the first circuit comprises

a first MOS transistor comprising a first drain connected to the first bitline, and a first gate connected to a first control signal;

a second MOS transistor comprising a source connected to the second bitline, and a second gate connected to a second control signal, and a second drain connected to a first source of the first MOS transistor;

a third MOS transistor comprising a third drain connected to the first power-supply voltage, a third gate connected to a third control signal, and a third source connected to the first source of the first MOS transistor; and

a fourth MOS transistor comprising a fourth source connected to the second power-supply voltage, a fourth gate connected to a fourth control signal, and a fourth drain connected to the first source of the first MOS transistor.

3. The ferroelectric memory of claim 1,

wherein each of the memory cells includes the ferroelectric capacitor and a cell transistor which are connected in parallel, and

wherein the memory cells are series-connected such that one terminal of which is connected to the first bitline or the second bitline via a block selection transistor.

4. The ferroelectric memory of claim 1,

wherein each of the memory cells includes the ferroelectric capacitor and a cell transistor which are connected in series, and

wherein one terminal of each of the memory cells at a side of the cell transistor is connected to the first bitline or the second bitline.

5. The ferroelectric memory of claim 1,

wherein the first and second bitlines are charged to the second power-supply voltage in a standby state, and

wherein the second bitline is set to the first power-supply voltage before the cell signal is read to the first bitline.

6. The ferroelectric memory of claim 1,

wherein the first and second bitlines are charged to the first power-supply voltage in a standby state, and

wherein the first bitline is set to the second power-supply voltage before the cell signal is read.

7. The ferroelectric memory of claim 1,

wherein the first power-supply voltage is a system power supply voltage, and

wherein the second power-supply voltage is a ground voltage.

8. The ferroelectric memory of claim 1,

wherein the first circuit is configured to set the second bitline to the second power-supply voltage before the second circuit sets the second bitline to the reference voltage to thereby increase a voltage difference applied on the ferroelectric capacitor during a read of the cell signal to the first bitline.

9. The ferroelectric memory of claim 1,

wherein the first circuit is configured to perform an overdrive on the ferroelectric capacitor.

16. A semiconductor chip comprising the ferroelectric memory of claim 1.

17. The semiconductor chip of claim 16, further comprising a CPU.

18. The semiconductor chip of claim 16, wherein the semiconductor chip has a system-on-chip structure.

10. A method for controlling a ferroelectric memory, the ferroelectric memory comprising a plurality of memory cells each including a ferroelectric memory and first and second bitlines configured to read cell signals from the memory cells, the method comprising:

fixing, when the cell signal is read from the memory cell to the first bitline, a voltage of the second bitline to a first power-supply voltage; and

setting the second bitline to a second power-supply voltage different from the first power-supply voltage;

reading the cell signal from the memory cell to the first bitline;

setting the second bitline to a reference voltage; and

amplifying a voltage difference between the first bitline to which the cell signal is read and the second bitline to which the reference voltage is set.

11. The method of claim 10,

wherein the first and second bitlines are charged to the second power-supply voltage in a standby state, and

wherein the second bitline is set to the first power-supply voltage before the cell signal is read out to the first bitline.

12. The method of claim 10,

wherein the first and second bitlines are charged to the first power-supply voltage in a standby state, and

wherein the first bitline is set to the second power-supply voltage before the cell signal is read out.

13. The method of claim 10,

wherein the first power-supply voltage is a system power supply voltage, and

wherein the second power-supply voltage is a ground voltage.

14. The method of claim 10,

wherein the second bitline is set to the second power-supply voltage in connection with a read of the cell signal from the memory cell to the first bitline to thereby increase a voltage difference applied on the ferroelectric capacitor during the read of the cell signal to the first bitline.

15. The method of claim 10,

wherein the second bitline is set to the second power-supply voltage in connection with a read of the cell signal from the memory cell to the first bitline to thereby perform an overdrive on the ferroelectric capacitor.