NON-UNIFORM SWITCHING BASED NON-VOLATILE MAGNETIC BASED MEMORY

• US 20120069649A1
• Filed: 11/28/2011
• Published: 03/22/2012
• Est. Priority Date: 10/20/2006
• Status: Active Grant

• Current Assignee: Avalanche Technology Incorporated
• Original Assignee: Avalanche Technology Incorporated
• Inventors: Ranjan, Rajiv Yadav, Estakhri, Petro, Assar, Mahmud, Keshtbod, Parviz
• Granted Patent: US 8,477,530 B2
• Time in Patent Office: Days
• US Class Current: 365/171
• CPC Class Codes: B82Y 10/00 Nanotechnology for information processing, storage or transmission, e.g. quantum computing or single electron logic
• CPC Class Codes: G11C 11/161 details concerning the memory cell structure, e.g. the layers of the ferromagnetic memory cell
• CPC Class Codes: G11C 11/1673 Reading or sensing circuits or methods
• CPC Class Codes: G11C 11/1675 Writing or programming circuits or methods
• CPC Class Codes: H10B 61/22 of the field-effect transistor [FET] type
• CPC Class Codes: H10N 50/10 Magnetoresistive devices

Abstract

A non-uniform switching based non-volatile magnetic memory element includes a fixed layer, a barrier layer formed on top of the fixed layer, a first free layer formed on top of the barrier layer, a non-uniform switching layer (NSL) formed on top of the first free layer, and a second free layer formed on top of the non-uniform switching layer. Switching current is applied, in a direction that is substantially perpendicular to the fixed layer, barrier layer, first free layer, non-uniform switching layer and the second free layer causing switching between states of the first free layer, second free layer and non-uniform switching layer with substantially reduced switching current.

Claims

1. A non-uniform switching based non-volatile magnetic memory element that is adapted to store information based on the direction of magnetization thereof when current is applied, the non-uniform switching based non-volatile magnetic memory element comprising:

a fixed layer having a magnetic moment that is fixed in direction;

a barrier layer formed on top of the fixed layer;

a first free layer formed on top of the barrier layer;

a non-uniform switching layer (NSL) formed on top of the first free layer; and

a second free layer formed on top of the NSL, the first free layer, the NSL, and the second free layer, the first and second free layer each having a magnetic moment that switches in direction relative to that of the fixed layer to store information in the non-uniform switching based non-volatile magnetic memory element, wherein when no switching current is applied to the second free layer, the net magnetization moment of the first and second free layers is aligned in a predetermined direction and the second free layer includes seeding areas that are scattered throughout the second free layer, the seeding areas each having a direction of magnetization moment, and when switching current is applied to the second free layer, the direction of magnetization moment of most of the seeding areas switches to a direction opposite to the predetermined direction, and when the switching current is increased, the seeding areas grow out to fuse to each other thereby leading to an avalanche type of switching to cause switching of the direction of the net magnetic moment of the first and second free layers.

2. A non-uniform switching based non-volatile magnetic memory element, as recited in claim 1, wherein the NSL is made of a mixture of magnetic and non-magnetic regions.

3. A non-uniform switching based non-volatile magnetic memory element, as recited in claim 1, further including more than one NSL formed on top of each other.

4. A non-uniform switching based non-volatile magnetic memory element, as recited in claim 1, wherein the NSL is comprised of micro-channels dispersed in the non-uniform switching layer.

5. A non-uniform switching based non-volatile magnetic memory element, as recited in claim 4, wherein the micro-channels are made substantially of a magnetic material.

6. A non-uniform switching based non-volatile magnetic memory element, as recited in claim 5, wherein the micro-channels are separated by a non-conductive material.

7. A non-uniform switching based non-volatile magnetic memory element, as recited in claim 6, wherein the second free layer has a thickness within the range of 1-10 nano meters.

8. A non-uniform switching based non-volatile magnetic memory element, as recited in claim 7, wherein the magnetic regions are each made substantially of CoFe.

9. A non-uniform switching based non-volatile magnetic memory element, as recited in claim 7, wherein the magnetic regions are each made substantially of material from a group consisting of:

CoFe, Ni, Co, Fe and a combination thereof

10. A non-uniform switching based non-volatile magnetic memory element, as recited in claim 7, wherein the non-conductive material are made substantially of material from a group consisting of:

TiO2, Al₂O₃, MgO, Ta₂O₅, HfO₂, ZrO₂, and TaN.

11. A non-uniform switching based non-volatile magnetic memory element, as recited in claim 1, wherein the second free layer has a thickness within the range of 1-10 nano meters.

12. A non-uniform switching based non-volatile magnetic memory element, as recited in claim 1, wherein switching current is lowered by 2 to 5 fold.

13. A non-uniform switching based non-volatile magnetic memory element, as recited in claim 1, wherein the first and second free layers each have a thickness and the thickness of the first free layer is at least as that of the free layer.

14. A non-uniform switching based non-volatile magnetic memory element, as recited in claim 1, wherein the first and second free layers each have a thickness and the thickness of the first free layer to that of the second free layer is 5 to 1.

15. A non-uniform switching based non-volatile magnetic memory element, as recited in claim 1, including a three dimensional memory structure formed of the memory elements stacked on top of each other.

16. A non-uniform switching based non-volatile magnetic memory element, as recited in claim 1, further including a top electrode formed on top of the second free layer.

17. A non-uniform switching based non-volatile magnetic memory element, as recited in claim 16, wherein the fixed layer includes a second fixed layer on top of which is formed a synthetic anti-ferromagnetic (AF) coupling layer on top of which is formed a third fixed layer.

18. A non-uniform switching based non-volatile magnetic memory element, as recited in claim 17, further including a bottom electrode on top of which is formed the fixed layer.

19. A non-uniform switching based non-volatile magnetic memory element, as recited in claim 1, wherein the first free layer is made of CoFeBCr.

20. A non-uniform switching based non-volatile magnetic memory element, as recited in claim 19, wherein the first free layer has a thickness within the range of 1-5 nano meters.

21. A non-uniform switching based non-volatile magnetic memory element, as recited in claim 20, wherein the magnetic regions of the NSL are made of CoFe and the non-magnetic regions of the NSL are made of TiO₂.

22. A non-uniform switching based non-volatile magnetic memory element, as recited in claim 1, wherein the NSL has a granular microstructure, which includes nano-particles made of magnetic and/or non-magnetic parts causing low-current switching due to the non-uniform switching associated therewith.

23. A non-uniform switching based non-volatile magnetic memory element, as recited in claim 1, wherein the non-uniform switching based non-volatile magnetic memory element is coupled, through an electrode, to a bit line, on one of its ends and on the other end, the memory element is coupled to a bottom electrode, through a contact, the contact being coupled to a drain of a transistor, which includes a source shown coupled to a program/erase line and the gate of the transistor being coupled to a word line.

24. A non-uniform switching based non-volatile magnetic memory element, as recited in claim 1, further including a sense amplifier circuit coupled to a first decoding transistor and further coupled to a second decoding transistor, at their source, the drain of the first decoding transistor being coupled to a reference memory element (MTJ), the reference memory element being further coupled to a third transistor at the drain of the transistor, the gate of the third transistor forming a reference word line and the source of the third transistor forming an erase voltage coupled to the source of a fourth transistor, the drain of the fourth transistor being coupled to a second memory element and an opposite end of the memory element being coupled to the drain of the second decode transistor to form a first bit line, the erase voltage being coupled to the source of a fifth transistor and the gate of the fifth transistor forming the second word line, the drain of the fifth transistor being coupled to a second memory element, which on an opposite end thereto, is coupled to form the second bit line.