Semiconductor Memory Having Both Volatile and Non-Volatile Functionality and Method of Operating

• US 20120069652A1
• Filed: 09/13/2011
• Published: 03/22/2012
• Est. Priority Date: 11/29/2006
• Status: Active Grant

• Current Assignee: Zeno Semiconductor, Inc.
• Original Assignee: Zeno Semiconductor, Inc.
• Inventors: Widjaja, Yuniarto
• Granted Patent: US 8,391,066 B2
• Time in Patent Office: Days
• US Class Current: 365/185.03
• CPC Class Codes: G11C 11/40 using transistors
• CPC Class Codes: G11C 11/404 with one charge-transfer gate, e.g. MOS transistor, per cell
• CPC Class Codes: G11C 14/0018 whereby the nonvolatile element is an EEPROM element, e.g. a floating gate or metal-nitride-oxide-silicon [MNOS] transistor
• CPC Class Codes: G11C 16/0416 comprising cells containing a single floating gate transistor and no select transistor, e.g. UV EPROM
• CPC Class Codes: G11C 2211/4016 Memory devices with silicon-on-insulator cells
• CPC Class Codes: H01L 29/66825 with a floating gate H01L29/6684 takes precedence
• CPC Class Codes: H01L 29/66833 with a charge trapping gate insulator, e.g. MNOS transistors
• CPC Class Codes: H01L 29/78 with field effect produced by an insulated gate H01L29/7725, H01L29/775, H01L29/778 take precedence
• CPC Class Codes: H01L 29/7841 with floating body, e.g. programmable transistors
• CPC Class Codes: H01L 29/7881 Programmable transistors with only two possible levels of programmation H01L29/7888 takes precedence
• CPC Class Codes: H10B 12/20 DRAM devices comprising floating-body transistors, e.g. floating-body cells

Abstract

Semiconductor memory having both volatile and non-volatile modes and methods of operation. A semiconductor memory cell includes a substrate, a floating body to store data in volatile memory and a floating gate or trapping layer configured to receive transfer of data stored by the volatile memory and store the data as nonvolatile memory in the floating gate or trapping layer upon interruption of power to the memory cell.

Claims

1-33. -33. (canceled)

34. A semiconductor memory cell comprising:

a floating body region configured to be charged to a level indicative of a state of the memory cell to store the state as volatile memory;

a first region in electrical contact with said floating body region;

a second region in electrical contact with said floating body region and spaced apart from said first region;

a floating gate or trapping layer positioned between said first and second regions and configured to receive transfer of data stored as said volatile memory and store said data as nonvolatile memory indicative of said state of the memory cell; and

a control gate positioned above the floating gate or trapping layer,

wherein said charge stored in said floating body region determines a charge stored in said floating gate or trapping layer upon interruption of power to the memory cell.

35. The semiconductor memory cell of claim 34, wherein said floating body region has a first conductivity type selected from a p-type conductivity type and an n-type conductivity type;

said first region has a second conductivity type selected from said p-type and n-type conductivity types, said second conductivity type being different from said first conductivity type; and

said second region has said second conductivity type.

36. The semiconductor memory cell of claim 34, wherein said transfer of data to said floating gate or trapping layer occurs in a non-algorithmic manner.

37. The semiconductor memory cell of claim 34, wherein said transfer of data to said floating gate or trapping layer occurs upon interruption of power to said memory cell.

38. The semiconductor memory cell of claim 37, wherein when power is restored to the cell, data transfer from the floating gate or trapping layer to the floating body occurs in a non-algorithmic manner, and the cell functions as volatile memory.

39. The semiconductor memory cell of claim 34, wherein the semiconductor memory cell functions as a binary cell.

40. The semiconductor memory cell of claim 34, wherein the semiconductor memory cell functions as a multi-level cell.

41. A semiconductor memory cell comprising:

a floating body region configured to be charged to a level indicative of a state of the memory cell to store the state as volatile memory;

a first region in electrical contact with said floating body region;

a second region in electrical contact with said floating body region and spaced apart from said first region;

a floating gate or trapping layer positioned between said first and second regions and configured to receive transfer of data stored as said volatile memory and store said data as nonvolatile memory indicative of said state of the memory cell; and

a control gate positioned above the floating gate or trapping layer,

wherein said state stored in said floating body region determines a current flowing through said semiconductor memory cell.

42. The semiconductor memory cell of claim 41, wherein said floating body region has a first conductivity type selected from a p-type conductivity type and an n-type conductivity type;

said first region has a second conductivity type selected from said p-type and n-type conductivity types, said second conductivity type being different from said first conductivity type; and

said second region has said second conductivity type.

43. The semiconductor memory cell of claim 41, wherein said floating gate or trapping layer receives transfer of said data upon interruption of power to the memory cell.

44. The semiconductor memory cell of claim 41, wherein said current flowing through said semiconductor memory cell determines the charge stored in said floating gate or trapping layer upon interruption of power to the memory cell.

45. The semiconductor memory cell of claim 41, wherein said transfer of data to said floating gate or trapping layer occurs in a non-algorithmic manner.

46. The semiconductor memory cell of claim 43, wherein when power is restored to the cell, data transfer from the floating gate or trapping layer to the floating body occurs in a non-algorithmic manner, and the cell functions as volatile memory.

47. The semiconductor memory cell of claim 41, wherein the semiconductor memory cell functions as a binary cell.

48. The semiconductor memory cell of claim 41, wherein the semiconductor memory cell functions as a multi-level cell.

49. A method of operating a memory cell to economize power usage, wherein the memory cell has a floating body for storing data as volatile memory and a floating gate or trapping layer for storing data as non-volatile memory, the method comprising:

monitoring activity of said cell; and

after a predetermined period of time during which said cell has remained idle, performing a shadowing operation thereby storing a state of the cell in non-volatile memory.

50. The method of claim 49, further comprising:

shutting down power to said memory cell.

51. The method of claim 49, further comprising:

shutting down power to the volatile memory of said floating body.

52. The method of claim 49, wherein said shadowing operation occurs in a non-algorithmic manner.

53. The method of claim 49, further comprising:

restoring a volatile memory state into said floating body when said volatile memory data is needed, wherein said volatile memory state is the same as a volatile memory state stored in said floating body before performing said shadowing operation.

54. A memory device comprising:

a plurality of semiconductor memory cells, each said memory cell having;

a floating body region configured to be charged to a level indicative of a state of the memory cell to store the state as volatile memory;

a first region in electrical contact with said floating body region;

a second region in electrical contact with said floating body region and spaced apart from said first region;

a floating gate or trapping layer positioned between said first and second regions and configured to receive transfer of data stored as said volatile memory and store said data as nonvolatile memory indicative of said state of the memory cell; and

a control gate positioned above the floating gate or trapping layer; and

wherein said transfer of data to said floating gate or trapping layer occurs in said memory cells in a parallel, non-algorithmic manner.