VARIABLE-LENGTH CODE DECODER

• US 20120070094A1
• Filed: 11/28/2011
• Published: 03/22/2012
• Est. Priority Date: 11/19/1999
• Status: Active Grant

• Current Assignee: ATI Technologies ULC (Advanced Micro Devices, Inc.)
• Original Assignee: ATI Technologies ULC (Advanced Micro Devices, Inc.)
• Inventors: Fogg, Chad E., Patwa, Nital P., Dalal, Parin B., Purcell, Stephen C., Van Dyke, Korbin, Hale, Steve C.
• Granted Patent: US 8,824,819 B2
• Time in Patent Office: Days
• US Class Current: 382/246
• CPC Class Codes: H04N 19/436 using parallelised computational arrangements
• CPC Class Codes: H04N 19/44 Decoders specially adapted therefor, e.g. video decoders which are asymmetric with respect to the encoder
• CPC Class Codes: H04N 19/61 in combination with predictive coding
• CPC Class Codes: H04N 19/91 Entropy coding, e.g. variable length coding [VLC] or arithmetic coding

Abstract

An apparatus includes at least one general purpose register and at least one special purpose register and an execution unit that executes at least two instructions in parallel, to decode variable length codes, wherein each of the instructions share use of the at least one general purpose register and the at least one special purpose register. In one example, a processor stores variable length code information among a plurality of general purpose registers and generates decoded variable length code information by decoding the at least one variable length code. The processor also stores the decoded variable length code information among the plurality of general purpose registers.

Claims

1. An apparatus comprising:

a processor operative to execute executable instructions that when executed by the processor cause the processor to;

store variable length code information among a plurality of general purpose registers;

generate decoded variable length code information by decoding the at least one variable length code; and

store the decoded variable length code information among the plurality of general purpose registers, wherein the variable length code information is associated with a number of macroblocks.

2. The apparatus of claim 1 wherein the locations of the general purpose registers in memory are dynamically allocated during run-time.

3. The apparatus of claim 1 wherein the variable length code information comprises MPEG-4 variable length code information.

4. The apparatus of claim 1, wherein the processor comprises a MIPS processor.

5. The apparatus of claim 1, wherein the apparatus comprises an MPEG decoder.

6. The apparatus of claim 1, wherein the processor comprises a RISC processor.

7. The apparatus of claim 1, wherein the macroblocks are comprised of both at least a luminance macroblock and a chrominance macroblock.

8. An apparatus comprising:

a processor operative to execute executable instructions that when executed by the processor cause the processor to;

store variable length code information among a plurality of general purpose registers;

generate decoded variable length code information by decoding the at least one variable length code; and

store the decoded variable length code information among the plurality of general purpose registers;

a storage device, operatively coupled to the processor, that stores the decoded variable length data.

9. The apparatus of claim 8 wherein the locations of the general purpose registers in memory are dynamically allocated during run-time.

10. The apparatus of claim 8 wherein the variable length code information comprises MPEG-4 variable length code information.

11. The apparatus of claim 8, wherein the processor comprises a MIPS processor.

12. The apparatus of claim 8, wherein the apparatus comprises an MPEG decoder.

13. The apparatus of claim 8, wherein the processor comprises a RISC processor.

14. The apparatus of claim 8, wherein the macroblocks are comprised of both at least a luminance macroblock and a chrominance macroblock.