SEMICONDUCTOR DEVICE AND FABRICATION METHOD THEREFOR

• US 20120070951A1
• Filed: 12/21/2010
• Published: 03/22/2012
• Est. Priority Date: 06/28/2005
• Status: Active Grant

• Current Assignee: Infineon Technologies Batam PT (Infineon Technologies AG)
• Original Assignee: Masaya Hosaka
• Inventors: HOSAKA, Masaya
• Granted Patent: US 8,530,307 B2
• Time in Patent Office: Days
• US Class Current: 438/287
• CPC Class Codes: H01L 21/76229 Concurrent filling of a plurality of trenches having a different trench shape or dimension, e.g. rectangular and V-shaped trenches, wide and narrow trenches, shallow and deep trenches
• CPC Class Codes: H10B 43/30 characterised by the memory core region
• CPC Class Codes: H10B 69/00 Erasable-and-programmable ROM [EPROM] devices not provided for in groups H10B41/00 - H10B63/00, e.g. ultraviolet erasable-and-programmable ROM [UVEPROM] devices

Abstract

There is provided a semiconductor device including bit lines (14) formed in a semiconductor substrate (10), insulating film lines (18) located on the bit lines (14) to successively run in a length direction of the bit lines (14), gate electrodes (16) located above the semiconductor substrate (10) between the bit lines (14), and word lines (20) located on the gate electrodes (18) to run in a width direction of the bit lines (14), a trench region (22) formed between the bit lines (14) and the between word lines (20) in the semiconductor substrate, and there is also provided a fabrication method therefor. According to the present invention, it is possible to provide a semiconductor device where elements can be isolated between the word lines (14) and memory cells can be miniaturized, and to provide a fabrication method therefor,

Claims

1. A semiconductor device comprising:

bit lines formed in e semiconductor substrate;

insulating film lines located on the bit lines to successively run in a length direction of the bit lines;

gate electrodes located above the semiconductor substrate between the bit lines; and

word lines located on the gate electrodes to run in a width direction of the bit lines;

a trench region formed between the bit fines and the between word lines in the semiconductor substrate.

2. The semiconductor device as claimed In claim 1, wherein side surfaces of the insulating film lines are substantially perpendicular to a surface of the semiconductor substrate.

3. The semiconductor device as claimed in claim 1, wherein each of the insulating film lines Includes silicon oxide film.

4. The semiconductor device as claimed in claim 1, further comprising an insulating film layer provided on the trench region.

5. The semiconductor device as claimed in claim 4, further comprising a barrier layer provided between the trench region and the insulating film layer,

wherein the insulating film layer includes a silicon nitride film, and the barrier layer includes a silicon oxide film.

6. The semiconductor device as claimed in claim 1, further comprising e channel-cut region formed in the semiconductor substrate in the trench region, the channel-cut region having en opposite type impurity to those of the bit fines,

7. The semiconductor device as claimed in claim 6, further comprising sidewalls formed on sides of the trench region.

8. The semiconductor devices as claimed in claim 1, wherein ONO films located between the semiconductor substrate and the gate electrodes.

9. A method of fabricating a semiconductor device comprising:

forming bit lines in a semiconductor substrate;

forming insulating film lines on the bit lines to successively run in a length direction of the bit lines;

forming gale electrodes above the semiconductor substrate between the bit lines;

forming word lines on the gate electrodes to run in a width direction of the bit lines; and

forming a trench region between the bit lines and between the word lines in the semiconductor substrate.

wherein forming the trench region includes etching the semiconductor substrate by using at least the insulating film lines as an etching mask.

10. The method as claimed in claims 9,

wherein forming the bit lines includes implanting ions in the semiconductor substrate having openings formed in a first metal, of which the gate electrodes are to be composed;

and

wherein forming the insulating Film lines includes forming a layer of the insulating film lines on the openings and on the first metal layer, and polishing the layer of the insulating film lines to the first metal layer.

11. The method as claimed in claims 9, wherein forming the insulating film lines includes forming a silicon oxide film by CVD.

12. The method as claimed in claims 9, further comprising forming an insulating film layer on the trench region.

13. The method as claimed in claim 12, further comprising forming a barrier layer that includes a silicon oxide film on the trench region,

wherein forming the insulating film layer includes forming a silicon nitride him on the barrier layer.

14. The method as claimed in claim 12, further comprising forming contact holes connected to the bit lines in the insulating film lines located between the insulating film layers.

15. The method as claimed in claims 9, further comprising forming a channel-cut region having on opposite type impurity to those of the bit lines, in the semiconductor substrate in the trench region.

16. The method as claimed in claim 15, wherein forming the channel-cut region includes implanting ions in the trench region by using the insulating film lines as a mask.

17. The method as claimed in claim 15, further comprising forming sidewalls on sides of the trench region,

wherein forming the channel-cut region includes implanting ions in the trench region by using the insulating lines, word lines, and the sidewalls as a mask.

18. The method as claimed in claims 9, further comprising forming an ONO film on the semiconductor substrate,

wherein forming the gate electrodes include forming the gate electrodes on the ONO film.

19. A wireless communications device, said wireless communications device comprising:

a flash memory comprising;

bit lines formed in a semiconductor substrate;

insulating film lines located on the bit lines to successively run in a length direction of the bit lines;

gate electrodes located above the semiconductor substrate between the hit lines;

word lines located on the gate electrodes to run in a width direction of the bit lines; and

a trench region formed between the bit lines and the between word lines in the semiconductor substrate;

a processor;

a communications component;

a transmitter;

a receiver; and

an antenna connected to the transmitter circuit and the receiver circuit.

20. The wireless communications device of claim 19, wherein said flash memory is NAND flash memory.

21. wireless communications device of claim 19, wherein said flash memory is NOR flash memory.

22. The wireless communications device of claim 19, wherein said flash memory utilizes mirrorbits technology.

23. A computing device comprising:

a processor;

an input component;

an output component;

a memory comprising;

a volatile memory; and

a flash memory comprising;

bit lines formed In a semiconductor substrate;

insulating film lines located on the bit lines to successively run in a length direction of the bit lines;

gate electrodes located above the semiconductor substrate between the bit lines;

word lines located on the gate electrodes to run in a width direction of the bit lines; and

a trench region formed between the bit lines and the between word lines in the semiconductor substrate.

24. The computing device of claim 23, wherein said computing device is a personal computer (PC).

25. The computing device of claim 23, wherein said computing device is a personal digital assistant (PDA).

26. The computing device of claim 23, wherein said computing device is a gaming system.

27. A portable media player comprising:

a processor;

a cache;

a user input component;

a coder-decoder component; and

a memory comprising;

a flash memory comprising;

bit lines formed in a semiconductor substrate;

insulating film lines located on the bit lines to successively run in a length direction of the bit lines;

gate electrodes located above the semiconductor substrate between the bit lines;

word lines located on the gate electrodes to run in a width direction of the bit lines; and

a trench region formed between the bit lines and the between word lines in the semiconductor substrate.

28. The portable media player of claim 27, wherein said portable media player is a portable music player.

29. The portable media player of claim 27, wherein said portable media player is a portable video player.