Hierarchical Power Management Circuit, Power Management Method Using the Same, and System on Chip Including the Hierarchical Power Management Circuit

• US 20120072743A1
• Filed: 09/15/2011
• Published: 03/22/2012
• Est. Priority Date: 09/20/2010
• Status: Active Grant

• Current Assignee: Samsung Electronics Co. Ltd.
• Original Assignee: Samsung Electronics Co. Ltd.
• Inventors: Lee, Jae Gon, Park, Bong Il, Kang, Moo Kyung
• Granted Patent: US 9,268,395 B2
• Time in Patent Office: Days
• US Class Current: 713/300
• CPC Class Codes: G06F 1/3287 by switching off individual functional units in the computer system
• CPC Class Codes: Y02D 10/00 Energy efficient computing, e.g. low power processors, power management or thermal management

Abstract

A hierarchical power management circuit includes N power management circuits respectively included in N power domains each including at least one intellectual property (IP), wherein N is a natural number greater than one. The i-th (1<i<N) power management circuit from among the N power management circuits manages supply of power to an (i+1)th power domain from among the N power domains in response to a power management request signal output from a first power management circuit from among the N power management circuits

Claims

1. A hierarchical power management circuit, comprising:

N power management circuits respectively included in N power domains each comprising at least one intellectual property (IP), wherein N is a natural number greater than one,

wherein an i-th (1<

i<

N) power management circuit from among the N power management circuits manages supply of power to an (i+1)th power domain from among the N power domains in response to a power management request signal output from a first power management circuit from among the N power management circuits.

2. The hierarchical power management circuit of claim 1, wherein the i-th power management circuit manages an operation of the at least one IP included in the i-th power domain in response an operation management request signal output from the first power management circuit.

3. The hierarchical power management circuit of claim 1, wherein the first power management circuit and the i-th power management circuit transmit and receive data to and from each other by using an asynchronous interface.

4. The hierarchical power management circuit of claim 3, wherein the asynchronous interface uses a handshake method.

5-8. -8. (canceled)

9. A system on chip (SoC) comprising:

N power domains each comprising at least one IP, wherein N is a natural number greater than one; and

N power management circuits included in the N power domains, respectively,

wherein an i-th (1<

i<

N) power management circuit from among the N power management circuits manages supply of power to an (i+1)th power domain from among the N power domains in response to a power management request signal output from a first power management circuit from among the N power management circuits.

10. The SoC of claim 9, wherein the i-th power management circuit manages an operation of the at least one IP included in the i-th power domain in response to an operation management request signal output from the first power management circuit.

11. The SoC of claim 10, wherein the first power management circuit and the i-th power management circuit transmit and receive data to and from each other by using an asynchronous interface.

12. The SoC of claim 11, wherein the asynchronous interface uses a handshake method.

13. A mobile device comprising:

the SoC of claim 9; and

a power supply, which supplies power to the SoC.

14. The mobile device of claim 13, wherein the i-th power management circuit manages an operation of the at least one IP included in the i-th power domain in response to an operation management request signal output from the first power management circuit.

15. The mobile device of claim 14, wherein the first power management circuit and the i-th power management circuit transmit and receive data to and from each other by using an asynchronous interface.

16. A hierarchical power management circuit, comprising:

N power management circuits respectively included in N power domains each comprising at least one intellectual property (IP), wherein N is a natural number greater than one,

wherein an i-th (1<

i<

N) power management circuit from among the N power management circuits manages an operation of the at least one IP included in an (i+1)th power domain from among the N power domains in response to an operation management request signal output from a first power management circuit from among the N power management circuits.

17. The hierarchical power management circuit of claim 16, wherein the i-th power management circuit manages supply of power to the (i+1)th power domain from among the N power domains in response to a power management request signal output from the first power management circuit.

18. The hierarchical power management circuit of claim 16, wherein the first power management circuit and the i-th power management circuit transmit and receive data to and from each other by using an asynchronous interface.

19. The hierarchical power management circuit of claim 18, wherein the asynchronous interface uses a handshake method.

20. The hierarchical power management circuit of claim 16, wherein the first power management circuit comprises a register that holds first status information indicating whether power is supplied to the power domains other than the power domain that includes the first power management circuit and/or second status information indicating whether each of the at least one IP is operating.