MEMORY TESTER AND COMPILER WHICH MATCHES A TEST PROGRAM
First Claim
1. A memory tester comprising:
- a first operation register to store a first operation variable;
a second operation register to store a second operation variable;
a first selector to output the first or second operation variables stored in the first and second operation registers, selectively, as a burst address operation variable, based on a selection signal,a first burst address generating circuit capable of generating a first burst address signal based on the first operation variable outputted from the first selector; and
.a second burst address generating circuit capable of generating a second burst address signal based on the second operation variable outputted from the first selector.
1 Assignment
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Accused Products
Abstract
According to one embodiment, a memory tester is provided. The memory tester has first and second operation registers, a first selector, and first and second burst address generating circuits. The first operation register stores a first operation variable. The second operation register stores a second operation variable. The first selector outputs the first and second operation variables stored in the first and second operation registers selectively, as a burst address operation variable, based on a selection signal. The first and second burst address generating circuits are capable of generating first and second burst address signals based on the first and second operation variables outputted from the first selector, respectively.
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Citations
10 Claims
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1. A memory tester comprising:
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a first operation register to store a first operation variable; a second operation register to store a second operation variable; a first selector to output the first or second operation variables stored in the first and second operation registers, selectively, as a burst address operation variable, based on a selection signal, a first burst address generating circuit capable of generating a first burst address signal based on the first operation variable outputted from the first selector; and
.a second burst address generating circuit capable of generating a second burst address signal based on the second operation variable outputted from the first selector. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8)
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9. A compiler which is capable of being executed by a computer, comprising:
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converting first and second operation variables described in one unit of test program into first and second burst address operation variables, respectively; generating a first source code including the obtained first burst address operation variable and generating a second source code including the obtained second burst address operation variable, the first source code being separated from the second source code; and compiling the first and second source codes and generating first and second object files, respectively. - View Dependent Claims (10)
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Specification