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REGULATING ATOMIC MEMORY OPERATIONS TO PREVENT DENIAL OF SERVICE ATTACK

  • US 20120072984A1
  • Filed: 09/22/2010
  • Published: 03/22/2012
  • Est. Priority Date: 09/22/2010
  • Status: Active Grant
First Claim
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1. A processor comprising:

  • a first core to execute instructions of a first thread and a second thread, the first core having a memory execution unit to handle requests for memory operations by the first and second threads and a regulator logic to prevent the first thread from execution of a second atomic memory operation after completion of a first atomic memory operation until a time window has passed since completion of the first atomic memory operation.

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