REGULATING ATOMIC MEMORY OPERATIONS TO PREVENT DENIAL OF SERVICE ATTACK
First Claim
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1. A processor comprising:
- a first core to execute instructions of a first thread and a second thread, the first core having a memory execution unit to handle requests for memory operations by the first and second threads and a regulator logic to prevent the first thread from execution of a second atomic memory operation after completion of a first atomic memory operation until a time window has passed since completion of the first atomic memory operation.
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Abstract
In one embodiment, the present invention includes a method for identifying a termination sequence for an atomic memory operation executed by a first thread, associating a timer with the first thread, and preventing the first thread from execution of a memory cluster operation after completion of the atomic memory operation until a prevention window has passed. This method may be executed by regulation logic associated with a memory execution unit of a processor, in some embodiments. Other embodiments are described and claimed.
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Citations
20 Claims
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1. A processor comprising:
a first core to execute instructions of a first thread and a second thread, the first core having a memory execution unit to handle requests for memory operations by the first and second threads and a regulator logic to prevent the first thread from execution of a second atomic memory operation after completion of a first atomic memory operation until a time window has passed since completion of the first atomic memory operation. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10)
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11. A method comprising:
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identifying a termination sequence for an atomic memory operation executed by a first thread; associating a timer with the first thread, the timer to count a period of a prevention window for the first thread; and preventing the first thread from execution of a memory cluster operation after completion of the atomic memory operation until the prevention window has passed. - View Dependent Claims (12, 13, 14, 15, 16, 17)
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18. A system comprising:
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a processor including at least one core to execute instructions, the at least one core including; a front end unit to fetch and decode an instruction; a renamer to associate at least one operand of the instruction with a physical register; an execution unit coupled to the front end unit to execute the instruction using the at least one operand; a memory execution unit (MEU) coupled to the execution unit to handle incoming memory requests from the execution unit; and a regulator coupled to the MEU to delay at least one atomic memory operation requested by a first thread from being provided to the MEU responsive to termination of a prior atomic memory operation requested by the first thread; and a dynamic random access memory (DRAM) coupled to processor. - View Dependent Claims (19, 20)
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Specification