3D MEMORY ARRAY WITH VERTICAL TRANSISTOR

• US 20120074466A1
• Filed: 09/28/2010
• Published: 03/29/2012
• Est. Priority Date: 09/28/2010
• Status: Abandoned Application

• Current Assignee: Seagate Technology LLC (Seagate Technology Holdings Plc)
• Original Assignee: Seagate Technology LLC (Seagate Technology Holdings Plc)
• Inventors: Setiadi, Dadi, Manos, Peter Nicholas, Liou, Hsing-Kuen, Kim, Young Pil, Lee, Hyung-Kyu, Khoury, Maroun Georges, Jung, Chulmin, Subramanian, Paramasivan Kamatchi
• Application Number:
  US12/891,982
• Publication Number:
  US 20120074466A1
• Time in Patent Office: Days
• US Class Current: 257/204
• CPC Class Codes: H01L 21/823487 with a particular manufacturing method of vertical transistor structures, i.e. with channel vertical to the substrate surface with a current flow parallel to the substrate surface H01L21/823431
• CPC Class Codes: H10B 61/22 of the field-effect transistor [FET] type
• CPC Class Codes: H10B 63/34 of the vertical channel field-effect transistor type
• CPC Class Codes: H10B 63/80 Arrangements comprising multiple bistable or multi-stable switching components of the same type on a plane parallel to the substrate, e.g. cross-point arrays
• CPC Class Codes: H10B 63/84 arranged in a direction perpendicular to the substrate, e.g. 3D cell arrays
• CPC Class Codes: H10B 99/00 Subject matter not provided for in other groups of this subclass

Abstract

A memory array includes a base circuitry layer and a plurality of memory array layers stacked sequentially to form the memory array. Each memory array layer is electrically coupled to the base circuitry layer. Each memory array layer includes a plurality of memory units. Each memory unit includes a vertical pillar transistor electrically coupled to a memory cell.

Claims

1. A memory array comprising:

a base circuitry layer;

a first memory array layer disposed on the base circuitry layer and electrically coupled to the base circuitry layer, the first memory array layer comprising a plurality of memory units, each memory unit comprising a vertical pillar transistor electrically coupled to a memory cell; and

a second memory array layer disposed on the first memory array layer and electrically coupled to the base circuitry layer, the second memory array layer comprising a plurality of memory units, each memory unit comprising a vertical pillar transistor electrically coupled to a memory cell.

2. The memory array according to claim 1 wherein the memory cells comprise STRAM memory cells.

3. The memory array according to claim 1 wherein the first memory array layer separates at least a portion of the second memory array layer from the base circuitry layer.

4. The memory array according to claim 1 further comprising three or more memory array layers stacked sequentially to form the memory array and wherein each memory array layer is electrically coupled to the base circuitry layer.

5. The memory array according to claim 1 wherein the first memory array layer is electrically isolated from the second memory array layer.

6. The memory array according to claim 1 wherein the first memory array layer and the second memory array layer includes a plurality of rows and columns of memory units.

7. The memory array according to claim 1 wherein the vertical pillar transistor of each memory unit has a drain, source and channel regions that are vertically stacked on top of each other and extending away from the base circuitry layer.

8. The memory array according to claim 4 wherein the base circuitry layer controls the memory units in all of the memory array layers.

9. A memory array comprising:

a base circuitry layer;

a plurality of memory array layers stacked sequentially to form the memory array and wherein each memory array layer is electrically coupled to the base circuitry layer, wherein each memory array layer comprises a plurality of memory units, each memory unit comprising a vertical pillar transistor electrically coupled to a memory cell.

10. The memory array according to claim 9 wherein the memory cells comprise STRAM memory cells.

11. The memory array according to claim 9 wherein the memory cells comprise RRAM memory cells.

12. The memory array according to claim 9 wherein the memory array layers are electrically isolated from each other.

13. The memory array according to claim 9 wherein the memory array layers include a plurality of rows and columns of memory units.

14. The memory array according to claim 9 wherein the vertical pillar transistor of each memory unit has a drain, source and channel regions that are vertically stacked on top of each other and extending away from the base circuitry layer.

15. The memory array according to claim 9 wherein the base circuitry layer controls the memory units in all of the memory array layers.

16. A method of forming a memory array comprising:

forming a first memory array layer on a base circuitry layer, the first memory array layer is electrically coupled to the base circuitry layer, wherein the first memory array layer comprises a plurality of memory units, each memory unit comprising a vertical pillar transistor electrically coupled to a memory cell;

disposing a semiconductor layer on the first memory array layer;

forming a second memory array layer from the semiconductor layer;

the second memory array layer is electrically coupled to the base circuitry layer, wherein the second memory array layer comprises a plurality of memory units, each memory unit comprising a vertical pillar transistor electrically coupled to a memory cell.

17. The method according to claim 16 further comprising forming a third memory array layer on the second memory array layer, the third memory array layer is electrically coupled to the base circuitry layer, wherein the second memory array layer comprises a plurality of memory units, each memory unit comprising a vertical pillar transistor electrically coupled to a STRAM memory cell.

18. The method according to claim 16 wherein the first and second memory array layers are electrically isolated from each other.

19. The method according to claim 16 further comprising controlling the memory units in the first and second memory array layers by the base circuitry layer.

20. The method according to claim 16 wherein the vertical pillar transistor of each memory unit has a drain, source and channel regions that are vertically stacked on top of each other and extending away from the base circuitry layer.