SEMICONDUCTOR PACKAGE WITH INTEGRATED METAL PILLARS AND MANUFACTURING METHODS THEREOF

• US 20120074532A1
• Filed: 04/12/2011
• Published: 03/29/2012
• Est. Priority Date: 09/27/2010
• Status: Active Grant

• Current Assignee: Advanced Semiconductor Engineering Inc (ASE Technology Holding Co., Ltd.)
• Original Assignee: Advanced Semiconductor Engineering Inc (ASE Technology Holding Co., Ltd.)
• Inventors: SHIH, MENG-KAI, LEE, CHANG-CHI
• Granted Patent: US 8,698,307 B2
• Time in Patent Office: Days
• US Class Current: 257/629
• CPC Class Codes: H01L 21/563 Encapsulation of active face of flip-chip device, e.g. underfilling or underencapsulation of flip-chip, encapsulation preform on chip or mounting substrate
• CPC Class Codes: H01L 2224/0401 Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
• CPC Class Codes: H01L 2224/05155 Nickel [Ni] as principal constituent
• CPC Class Codes: H01L 2224/05166 Titanium [Ti] as principal constituent
• CPC Class Codes: H01L 2224/05171 Chromium [Cr] as principal constituent
• CPC Class Codes: H01L 2224/05552 in top view
• CPC Class Codes: H01L 2224/05572 the external layer extending out of an opening
• CPC Class Codes: H01L 2224/05644 Gold [Au] as principal constituent
• CPC Class Codes: H01L 2224/05647 Copper [Cu] as principal constituent
• CPC Class Codes: H01L 2224/13027 the bump connector being offset with respect to the bonding area, e.g. bond pad
• CPC Class Codes: H01L 2224/13076 being mutually engaged together, e.g. through inserts
• CPC Class Codes: H01L 2224/1308 being stacked
• CPC Class Codes: H01L 2224/13083 Three-layer arrangements
• CPC Class Codes: H01L 2224/13139 Silver [Ag] as principal constituent
• CPC Class Codes: H01L 2224/13144 Gold [Au] as principal constituent
• CPC Class Codes: H01L 2224/13147 Copper [Cu] as principal constituent
• CPC Class Codes: H01L 2224/13155 Nickel [Ni] as principal constituent
• CPC Class Codes: H01L 2224/13171 Chromium [Cr] as principal constituent
• CPC Class Codes: H01L 2224/14104 relative to the bonding areas, e.g. bond pads, of the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/16105 the bump connector connecting bonding areas being not aligned with respect to each other
• CPC Class Codes: H01L 2224/16225 : the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/16227 : the bump connector connecting to a bond pad of the item
• CPC Class Codes: H01L 2224/16237 : the bump connector connecting to a bonding area disposed in a recess of the surface of the item
• CPC Class Codes: H01L 2224/73204 : the bump connector being embedded into the layer connector
• CPC Class Codes: H01L 2224/8114 : Guiding structures outside the body
• CPC Class Codes: H01L 23/3171 : the coating being directly applied to the semiconductor body, e.g. passivation layer H01L23/3178 takes precedence
• CPC Class Codes: H01L 23/49894 : Materials of the insulating layers or coatings
• CPC Class Codes: H01L 24/14 : of a plurality of bump connectors
• CPC Class Codes: H01L 24/16 : of an individual bump connector
• CPC Class Codes: H01L 24/17 : of a plurality of bump connectors
• CPC Class Codes: H01L 2924/00 : Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00012 : Relevant to the scope of the group, the symbol of which is combined with the symbol of this group
• CPC Class Codes: H01L 2924/00014 : the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/01005 : Boron [B]
• CPC Class Codes: H01L 2924/01019 : Potassium [K]
• CPC Class Codes: H01L 2924/01023 : Vanadium [V]
• CPC Class Codes: H01L 2924/01024 : Chromium [Cr]
• CPC Class Codes: H01L 2924/01029 : Copper [Cu]
• CPC Class Codes: H01L 2924/01033 : Arsenic [As]
• CPC Class Codes: H01L 2924/01047 : Silver [Ag]
• CPC Class Codes: H01L 2924/01074 : Tungsten [W]
• CPC Class Codes: H01L 2924/01075 : Rhenium [Re]
• CPC Class Codes: H01L 2924/01079 : Gold [Au]
• CPC Class Codes: H01L 2924/014 : Solder alloys
• CPC Class Codes: H01L 2924/10253 : Silicon [Si]

Abstract

A semiconductor package includes a substrate and a semiconductor device. The semiconductor device includes a body having a center, a layer disposed adjacent to the body, and a plurality of conductive pillars configured to electrically connect the semiconductor device to the substrate. The layer defines a plurality of openings. Each of the plurality of conductive pillars extends at least partially through a corresponding one of the plurality of openings. An offset between a first central axis of the each of the plurality of conductive pillars and a second central axis of the corresponding one of the plurality of openings varies with distance between the first central axis and the center of the body. The second central axis of the corresponding one of the plurality of openings is disposed between the first central axis of the each of the plurality of conductive pillars and the center of the body.

Claims

1. A semiconductor package, comprising:

a substrate; and

a semiconductor device comprising;

a body having a center;

a first layer disposed adjacent to the body, wherein the first layer defines a plurality of openings; and

a plurality of conductive pillars configured to electrically connect the semiconductor device to the substrate, each of the plurality of conductive pillars extending at least partially through a corresponding one of the plurality of openings;

wherein an offset between a first central axis of the each of the plurality of conductive pillars and a second central axis of the corresponding one of the plurality of openings varies with distance between the first central axis and the center of the body; and

wherein the second central axis of the corresponding one of the plurality of openings is disposed between the first central axis of the each of the plurality of conductive pillars and the center of the body.

2. The semiconductor package of claim 1, wherein the offset between the first central axis of the each of the plurality of conductive pillars and a second central axis of the corresponding one of the plurality of openings increases with distance between the first central axis and the center of the body.

3. The semiconductor package of claim 1, wherein the semiconductor device further comprises a second layer disposed between the body and the first layer, the second layer being a dielectric layer having a dielectric constant less than 2.5.

4. The semiconductor package of claim 3, wherein the offset between the first central axis of the each of the plurality of conductive pillars and the second central axis of the corresponding one of the plurality of openings is configured to reduce a maximum stress on the second layer to protect the second layer from at least one of cracking and delamination.

5. The semiconductor package of claim 1, wherein:

the plurality of openings include a first opening and a second opening;

the plurality of conductive pillars include a first conductive pillar corresponding to the first opening and a second conductive pillar corresponding to the second opening;

a first offset is a first distance between a central axis of the first conductive pillar and a central axis of the first opening;

a second offset is a second distance between a central axis of the second conductive pillar and a central axis of the second opening;

a third distance between the first conductive pillar and the center of the body is greater than a fourth distance between the second conductive pillar and the center of the body; and

the first offset is greater than the second offset.

6. The semiconductor package of claim 1, wherein:

an opening included in the plurality of openings has a first diameter;

a conductive pillar included in the plurality of conductive pillars and corresponding to the opening has a second diameter; and

the second diameter is at least twice as large as the first diameter.

7. The semiconductor package of claim 1, wherein:

a conductive pillar included in the plurality of conductive pillars defines a cavity; and

a metallic material softer than a material forming the conductive pillar is disposed in the cavity.

8. A semiconductor package, comprising:

a substrate; and

a semiconductor device comprising;

a body;

a pad disposed adjacent to the body;

a first layer disposed adjacent to the body, wherein the first layer defines an opening having a first diameter and exposing the pad; and

a conductive interconnect electrically connected to the pad and extending at least partially into the opening, wherein the conductive interconnect has a second diameter, and the second diameter is at least twice as large as the first diameter.

9. The semiconductor package of claim 8, wherein:

the body has a center; and

a first central axis of the opening is disposed between a second central axis of the conductive interconnect and the center of the body.

10. The semiconductor package of claim 8, wherein:

the semiconductor package has a lateral surface proximate to a first central axis of the conductive interconnect; and

the first central axis of the conductive interconnect is disposed between a second central axis of the opening and the lateral surface.

11. The semiconductor package of claim 8, wherein the semiconductor device further comprises a second layer disposed between the body and the first layer, the second layer being a dielectric layer having a dielectric constant less than 2.0.

12. The semiconductor package of claim 8, wherein:

the conductive interconnect defines a cavity; and

a first material softer than a second material forming the conductive interconnect is disposed in the cavity.

13. The semiconductor package of claim 12, wherein the semiconductor device further comprises a barrier layer disposed adjacent to the cavity.

14. The semiconductor package of claim 12, wherein the cavity is aligned with the opening.

15. A semiconductor package, comprising:

a substrate; and

a semiconductor device comprising;

a body;

a dielectric layer disposed adjacent to the body, wherein the dielectric layer is subject to stress resulting from a mismatch of coefficient of thermal expansion (CTE) between the substrate and the semiconductor device; and

means for reducing a maximum stress on the dielectric layer to protect the dielectric layer from at least one of cracking and delamination.

16. The semiconductor package of claim 15, wherein:

the semiconductor device includes a passivation layer disposed adjacent to the body, wherein the passivation layer defines an opening having a first diameter; and

the means for reducing the maximum stress on the dielectric layer includes a conductive interconnect extending at least partially into the opening, wherein the conductive interconnect has a second diameter, and the second diameter is at least twice as large as the first diameter.

17. The semiconductor package of claim 15, wherein the means for reducing a maximum stress on the dielectric layer includes a conductive pillar that defines a cavity filled with a first material softer than a second material forming the conductive pillar.

18. The semiconductor package of claim 15, wherein:

the body has a center;

the semiconductor device includes a layer disposed adjacent to the body, wherein the layer defines an opening; and

the means for reducing a maximum stress on the dielectric layer includes a conductive pillar extending at least partially through the opening;

wherein a first central axis of the opening is disposed between the center of the body and a second central axis of the conductive pillar.

19. The semiconductor package of claim 15, wherein:

the body has a center;

the semiconductor device includes a layer disposed adjacent to the body, wherein the layer defines a plurality of openings; and

the means for reducing a maximum stress on the dielectric layer includes a plurality of conductive pillars extending at least partially through a corresponding one of the plurality of openings;

wherein an offset between a first central axis of each of the plurality of conductive pillars and a second central axis of the corresponding one of the plurality of openings varies with distance between the first central axis and the center of the body; and

wherein the second central axis of the corresponding one of the plurality of openings is disposed between the first central axis of the each of the plurality of conductive pillars and the center of the body.

20. The semiconductor package of claim 19, wherein the offset between the first central axis of the each of the plurality of conductive pillars and the second central axis of the corresponding one of the plurality of openings increases with increasing distance between the first central axis and the center of the body.