Semiconductor Device and Method of Forming TSV Interposer With Semiconductor Die and Build-Up Interconnect Structure on Opposing Surfaces of the Interposer

• US 20120074585A1
• Filed: 07/15/2011
• Published: 03/29/2012
• Est. Priority Date: 09/24/2010
• Status: Active Grant

• Current Assignee: Stats Chippac Pte. Ltd. (JCET Group Co., Ltd.)
• Original Assignee: Stats Chippac Limited
• Inventors: Koo, Jun Mo, Marimuthu, Pandi Chelvam, Ku, Jae Hun, Yoon, Seung Wook
• Granted Patent: US 9,224,647 B2
• Time in Patent Office: Days
• US Class Current: 257/774
• CPC Class Codes: H01L 21/486 Via connections through the substrate with or without pins
• CPC Class Codes: H01L 21/561 Batch processing
• CPC Class Codes: H01L 21/568 Temporary substrate used as encapsulation process aid H01L21/4832 and H01L21/566 take precedence
• CPC Class Codes: H01L 21/76898 formed through a semiconductor substrate
• CPC Class Codes: H01L 2224/0345 Physical vapour deposition [PVD], e.g. evaporation, or sputtering
• CPC Class Codes: H01L 2224/03452 Chemical vapour deposition [CVD], e.g. laser CVD
• CPC Class Codes: H01L 2224/03464 Electroless plating
• CPC Class Codes: H01L 2224/0401 Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
• CPC Class Codes: H01L 2224/05009 Bonding area integrally formed with a via connection of the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/05552 in top view
• CPC Class Codes: H01L 2224/0557 the external layer being disposed on a via connection of the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/05611 Tin [Sn] as principal constituent
• CPC Class Codes: H01L 2224/05624 Aluminium [Al] as principal constituent
• CPC Class Codes: H01L 2224/05639 Silver [Ag] as principal constituent
• CPC Class Codes: H01L 2224/05644 Gold [Au] as principal constituent
• CPC Class Codes: H01L 2224/05647 Copper [Cu] as principal constituent
• CPC Class Codes: H01L 2224/05655 Nickel [Ni] as principal constituent
• CPC Class Codes: H01L 2224/06181 On opposite sides of the body
• CPC Class Codes: H01L 2224/13111 Tin [Sn] as principal constituent
• CPC Class Codes: H01L 2224/13113 Bismuth [Bi] as principal constituent
• CPC Class Codes: H01L 2224/13116 : Lead [Pb] as principal constituent
• CPC Class Codes: H01L 2224/13124 : Aluminium [Al] as principal constituent
• CPC Class Codes: H01L 2224/13139 : Silver [Ag] as principal constituent
• CPC Class Codes: H01L 2224/13144 : Gold [Au] as principal constituent
• CPC Class Codes: H01L 2224/13147 : Copper [Cu] as principal constituent
• CPC Class Codes: H01L 2224/13155 : Nickel [Ni] as principal constituent
• CPC Class Codes: H01L 2224/16145 : the bodies being stacked
• CPC Class Codes: H01L 2224/16146 : the bump connector connecting to a via connection in the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/16225 : the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/16227 : the bump connector connecting to a bond pad of the item
• CPC Class Codes: H01L 2224/16235 : the bump connector connecting to a via metallisation of the item
• CPC Class Codes: H01L 2224/32225 : the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/48091 : Arched
• CPC Class Codes: H01L 2224/73204 : the bump connector being embedded into the layer connector
• CPC Class Codes: H01L 2224/73265 : Layer and wire connectors
• CPC Class Codes: H01L 2224/81 : using a bump connector
• CPC Class Codes: H01L 2224/81192 : wherein the bump connectors are disposed only on another item or body to be connected to the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/81201 : Compression bonding
• CPC Class Codes: H01L 2224/81411 : Tin [Sn] as principal constituent
• CPC Class Codes: H01L 2224/81424 : Aluminium [Al] as principal constituent
• CPC Class Codes: H01L 2224/81439 : Silver [Ag] as principal constituent
• CPC Class Codes: H01L 2224/81444 : Gold [Au] as principal constituent
• CPC Class Codes: H01L 2224/81447 : Copper [Cu] as principal constituent
• CPC Class Codes: H01L 2224/81455 : Nickel [Ni] as principal constituent
• CPC Class Codes: H01L 2224/81815 : Reflow soldering
• CPC Class Codes: H01L 2224/83 : using a layer connector
• CPC Class Codes: H01L 2224/92125 : the second connecting process involving a layer connector
• CPC Class Codes: H01L 2224/97 : the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
• CPC Class Codes: H01L 2225/06513 : Bump or bump-like direct electrical connections between devices, e.g. flip-chip connection, solder bumps
• CPC Class Codes: H01L 2225/06517 : Bump or bump-like direct electrical connections from device to substrate
• CPC Class Codes: H01L 2225/06541 : Conductive via connections through the device, e.g. vertical interconnects, through silicon via [TSV]
• CPC Class Codes: H01L 2225/06548 : Conductive via connections through the substrate, container, or encapsulation
• CPC Class Codes: H01L 2225/1023 : the support being an insulating substrate
• CPC Class Codes: H01L 2225/1058 : Bump or bump-like electrical connections, e.g. balls, pillars, posts
• CPC Class Codes: H01L 23/147 : Semiconductor insulating substrates semiconductor conductive substrates H01L23/4926
• CPC Class Codes: H01L 23/3128 : the substrate having spherical bumps for external connection
• CPC Class Codes: H01L 23/49816 : Spherical bumps on the substrate for external connection, e.g. ball grid arrays [BGA]
• CPC Class Codes: H01L 23/49827 : Via connections through the substrates, e.g. pins going through the substrate, coaxial cables H01L23/49822, H01L23/49833, H01L23/4985, H01L23/49861 take precedence
• CPC Class Codes: H01L 23/49833 : the chip support structure consisting of a plurality of insulating substrates
• CPC Class Codes: H01L 24/05 : of an individual bonding area
• CPC Class Codes: H01L 24/06 : of a plurality of bonding areas
• CPC Class Codes: H01L 24/13 : of an individual bump connector
• CPC Class Codes: H01L 24/16 : of an individual bump connector
• CPC Class Codes: H01L 24/73 : Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
• CPC Class Codes: H01L 24/81 : using a bump connector
• CPC Class Codes: H01L 24/92 : Specific sequence of method steps
• CPC Class Codes: H01L 24/97 : the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
• CPC Class Codes: H01L 25/0652 : the devices being arranged next and on each other, i.e. mixed assemblies
• CPC Class Codes: H01L 25/0655 : the devices being arranged next to each other
• CPC Class Codes: H01L 25/0657 : Stacked arrangements of devices
• CPC Class Codes: H01L 25/105 : the devices being of a type provided for in group H01L27/00
• CPC Class Codes: H01L 25/18 : the devices being of types provided for in two or more different subgroups of the same main group of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N
• CPC Class Codes: H01L 25/50 : Multistep manufacturing processes of assemblies consisting of devices, each device being of a type provided for in group H01L27/00 or H01L29/00 H01L21/50 takes precedence
• CPC Class Codes: H01L 2924/00 : Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00012 : Relevant to the scope of the group, the symbol of which is combined with the symbol of this group
• CPC Class Codes: H01L 2924/00014 : the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/01322 : Eutectic Alloys, i.e. obtained by a liquid transforming into two solid phases
• CPC Class Codes: H01L 2924/12041 : LED
• CPC Class Codes: H01L 2924/12042 : LASER
• CPC Class Codes: H01L 2924/13091 : Metal-Oxide-Semiconductor Field-Effect Transistor [MOSFET]
• CPC Class Codes: H01L 2924/14 : Integrated circuits
• CPC Class Codes: H01L 2924/1431 : Logic devices
• CPC Class Codes: H01L 2924/1433 : Application-specific integrated circuit [ASIC]
• CPC Class Codes: H01L 2924/14335 : Digital signal processor [DSP]
• CPC Class Codes: H01L 2924/1434 : Memory
• CPC Class Codes: H01L 2924/15311 : being a ball array, e.g. BGA
• CPC Class Codes: H01L 2924/181 : Encapsulation
• CPC Class Codes: H01L 2924/19041 : being a capacitor
• CPC Class Codes: H01L 2924/19042 : being an inductor
• CPC Class Codes: H01L 2924/19043 : being a resistor
• CPC Class Codes: H01L 2924/19105 : in a side-by-side arrangement on a common die mounting substrate
• CPC Class Codes: H01L 2924/3511 : Warping

Abstract

A semiconductor device has a substrate with first and second opposing surfaces. A plurality of conductive vias is formed partially through the first surface of the substrate. A first conductive layer is formed over the first surface of the substrate electrically connected to the conductive vias. A first semiconductor die is mounted over the first surface of the substrate. The first semiconductor die and substrate are mounted to a carrier. An encapsulant is deposited over the first semiconductor die, substrate, and carrier. A portion of the second surface of the substrate is removed to expose the conductive vias. An interconnect structure is formed over a surface of the substrate opposite the first semiconductor die. A second semiconductor die can be stacked over the first semiconductor die. A second semiconductor die can be mounted over the first surface of the substrate adjacent to the first semiconductor die.

Claims

1. A method of making a semiconductor device, comprising:

providing a substrate having first and second opposing surfaces;

forming a plurality of conductive vias partially through the first surface of the substrate;

forming a first conductive layer over the first surface of the substrate electrically connected to the conductive vias;

mounting a first semiconductor die over the first surface of the substrate electrically connected to the first conductive layer;

providing a carrier;

mounting the first semiconductor die and substrate to the carrier;

depositing an encapsulant over the first semiconductor die, substrate, and carrier;

removing a portion of the second surface of the substrate to expose the conductive vias; and

forming an interconnect structure over a surface of the substrate opposite the first semiconductor die.

2. The method of claim 1, further including:

forming a first insulating layer over the first surface of the substrate prior to mounting the first semiconductor die; and

forming a plurality of bumps over the first conductive layer.

3. The method of claim 1, further including depositing an underfill material beneath the first semiconductor die.

4. The method of claim 1, further including stacking a second semiconductor die over the first semiconductor die.

5. The method of claim 1, further including stacking a plurality of second semiconductor die over the first semiconductor die.

6. The method of claim 1, further including mounting a second semiconductor die over the first surface of the substrate adjacent to the first semiconductor die.

7. A method of making a semiconductor device, comprising:

providing a substrate having first and second opposing surfaces;

forming a plurality of conductive vias within the substrate;

mounting a first semiconductor die over the first surface of the substrate;

providing a carrier;

mounting the first semiconductor die and substrate to the carrier;

depositing an encapsulant over the first semiconductor die, substrate, and carrier; and

forming an interconnect structure over the second surface of the substrate opposite the first semiconductor die.

8. The method of claim 7, further including:

forming the plurality of conductive vias partially through the first surface of the substrate; and

removing a portion of the second surface of the substrate to expose the conductive vias.

9. The method of claim 7, further including:

forming a first conductive layer over the first surface of the substrate electrically connected to the conductive vias prior to mounting the first semiconductor die; and

forming a first insulating layer over the first surface of the substrate.

10. The method of claim 7, further including stacking a second semiconductor die over the first semiconductor die.

11. The method of claim 10, wherein the second semiconductor die includes a memory circuit.

12. The method of claim 7, further including mounting a discrete semiconductor device over the substrate.

13. The method of claim 7, further including mounting a second semiconductor die over the first surface of the substrate adjacent to the first semiconductor die.

14. A method of making a semiconductor device, comprising:

providing a substrate;

forming a plurality of conductive vias within the substrate;

mounting a first semiconductor die over a first surface of the substrate;

depositing an encapsulant over the first semiconductor die and substrate; and

forming an interconnect structure over a second surface of the substrate opposite the first semiconductor die.

15. The method of claim 14, further including:

forming the plurality of conductive vias partially through the first surface of the substrate; and

removing a portion of the second surface of the substrate to expose the conductive vias.

16. The method of claim 14, further including:

forming a first conductive layer over the first surface of the substrate electrically connected to the conductive vias prior to mounting the first semiconductor die; and

forming a first insulating layer over the first surface of the substrate.

17. The method of claim 14, further including stacking a second semiconductor die over the first semiconductor die.

18. The method of claim 14, further including forming a plurality of conductive vias through the first semiconductor die.

19. The method of claim 14, wherein the second semiconductor die includes a memory circuit.

20. The method of claim 14, further including mounting a second semiconductor die over the first surface of the substrate adjacent to the first semiconductor die.

21. A semiconductor device, comprising:

a substrate;

a plurality of conductive vias formed within the substrate;

a first semiconductor die mounted over a first surface of the substrate;

an encapsulant deposited over the first semiconductor die and substrate; and

an interconnect structure formed over a second surface of the substrate opposite the first semiconductor die.

22. The semiconductor device of claim 21, wherein the plurality of conductive vias is formed partially through the first surface of the substrate and a portion of the second surface of the substrate is removed to expose the conductive vias.

23. The semiconductor device of claim 21, further including a second semiconductor die mounted over the first semiconductor die.

24. The semiconductor device of claim 21, wherein the second semiconductor die includes a memory circuit.

25. The semiconductor device of claim 21, further including a second semiconductor die mounted over the first surface of the substrate adjacent to the first semiconductor die.