Semiconductor Device and Method of Bonding Different Size Semiconductor Die at the Wafer Level

• US 20120074587A1
• Filed: 09/13/2011
• Published: 03/29/2012
• Est. Priority Date: 09/29/2010
• Status: Active Grant

• Current Assignee: Stats Chippac Pte. Ltd. (JCET Group Co., Ltd.)
• Original Assignee: Stats Chippac Limited
• Inventors: Koo, Jun Mo, Marimuthu, Pandi C., Yoon, Seung Wook, Shim, Il Kwon
• Granted Patent: US 8,993,377 B2
• Time in Patent Office: Days
• US Class Current: 257/774
• CPC Class Codes: H01L 21/561 Batch processing
• CPC Class Codes: H01L 21/563 Encapsulation of active face of flip-chip device, e.g. underfilling or underencapsulation of flip-chip, encapsulation preform on chip or mounting substrate
• CPC Class Codes: H01L 21/565 Moulds
• CPC Class Codes: H01L 21/568 Temporary substrate used as encapsulation process aid H01L21/4832 and H01L21/566 take precedence
• CPC Class Codes: H01L 21/6835 using temporarily an auxiliary support
• CPC Class Codes: H01L 21/76898 formed through a semiconductor substrate
• CPC Class Codes: H01L 2221/68327 used during dicing or grinding
• CPC Class Codes: H01L 2221/68381 Details of chemical or physical process used for separating the auxiliary support from a device or wafer
• CPC Class Codes: H01L 2221/68386 Separation by peeling
• CPC Class Codes: H01L 2224/0231 Manufacturing methods of the redistribution layers
• CPC Class Codes: H01L 2224/02313 Subtractive methods
• CPC Class Codes: H01L 2224/02317 by local deposition
• CPC Class Codes: H01L 2224/02372 connecting to a via connection in the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/02381 Side view
• CPC Class Codes: H01L 2224/0239 Material of the redistribution layers
• CPC Class Codes: H01L 2224/024 Material of the insulating layers therebetween
• CPC Class Codes: H01L 2224/0345 Physical vapour deposition [PVD], e.g. evaporation, or sputtering
• CPC Class Codes: H01L 2224/03452 Chemical vapour deposition [CVD], e.g. laser CVD
• CPC Class Codes: H01L 2224/03462 Electroplating
• CPC Class Codes: H01L 2224/03464 Electroless plating
• CPC Class Codes: H01L 2224/0401 : Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
• CPC Class Codes: H01L 2224/04042 : Bonding areas specifically adapted for wire connectors, e.g. wirebond pads
• CPC Class Codes: H01L 2224/05611 : Tin [Sn] as principal constituent
• CPC Class Codes: H01L 2224/05624 : Aluminium [Al] as principal constituent
• CPC Class Codes: H01L 2224/05639 : Silver [Ag] as principal constituent
• CPC Class Codes: H01L 2224/05644 : Gold [Au] as principal constituent
• CPC Class Codes: H01L 2224/05647 : Copper [Cu] as principal constituent
• CPC Class Codes: H01L 2224/05655 : Nickel [Ni] as principal constituent
• CPC Class Codes: H01L 2224/06131 : being uniform, i.e. having a uniform pitch across the array
• CPC Class Codes: H01L 2224/1132 : Screen printing, i.e. using a stencil
• CPC Class Codes: H01L 2224/11334 : using preformed bumps
• CPC Class Codes: H01L 2224/1134 : Stud bumping, i.e. using a wire-bonding apparatus
• CPC Class Codes: H01L 2224/1145 : Physical vapour deposition [PVD], e.g. evaporation, or sputtering
• CPC Class Codes: H01L 2224/11462 : Electroplating
• CPC Class Codes: H01L 2224/11464 : Electroless plating
• CPC Class Codes: H01L 2224/11849 : Reflowing
• CPC Class Codes: H01L 2224/11901 : with repetition of the same manufacturing step
• CPC Class Codes: H01L 2224/12105 : Bump connectors formed on an encapsulation of the semiconductor or solid-state body, e.g. bumps on chip-scale packages
• CPC Class Codes: H01L 2224/13025 : the bump connector being disposed on a via connection of the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/131 : with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
• CPC Class Codes: H01L 2224/13111 : Tin [Sn] as principal constituent
• CPC Class Codes: H01L 2224/13113 : Bismuth [Bi] as principal constituent
• CPC Class Codes: H01L 2224/13116 : Lead [Pb] as principal constituent
• CPC Class Codes: H01L 2224/13124 : Aluminium [Al] as principal constituent
• CPC Class Codes: H01L 2224/13139 : Silver [Ag] as principal constituent
• CPC Class Codes: H01L 2224/13144 : Gold [Au] as principal constituent
• CPC Class Codes: H01L 2224/13147 : Copper [Cu] as principal constituent
• CPC Class Codes: H01L 2224/13155 : Nickel [Ni] as principal constituent
• CPC Class Codes: H01L 2224/1403 : Bump connectors having different sizes, e.g. different diameters, heights or widths
• CPC Class Codes: H01L 2224/14181 : On opposite sides of the body
• CPC Class Codes: H01L 2224/16146 : the bump connector connecting to a via connection in the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/1703 : Bump connectors having different sizes, e.g. different diameters, heights or widths
• CPC Class Codes: H01L 2224/17181 : On opposite sides of the body
• CPC Class Codes: H01L 2224/21 : of an individual HDI interconnect
• CPC Class Codes: H01L 2224/2105 : Shape
• CPC Class Codes: H01L 2224/215 : Material
• CPC Class Codes: H01L 2224/22 : of a plurality of HDI interconnects
• CPC Class Codes: H01L 2224/221 : Disposition
• CPC Class Codes: H01L 2224/2518 : being disposed on at least two different sides of the body, e.g. dual array
• CPC Class Codes: H01L 2224/29144 : Gold [Au] as principal constituent
• CPC Class Codes: H01L 2224/2919 : with a principal constituent of the material being a polymer, e.g. polyester, phenolic based polymer, epoxy
• CPC Class Codes: H01L 2224/48105 : Connecting bonding areas at different heights
• CPC Class Codes: H01L 2224/48175 : the item being metallic
• CPC Class Codes: H01L 2224/48227 : connecting the wire to a bond pad of the item
• CPC Class Codes: H01L 2224/48228 : the bond pad being disposed in a recess of the surface of the item
• CPC Class Codes: H01L 2224/73204 : the bump connector being embedded into the layer connector
• CPC Class Codes: H01L 2224/73259 : Bump and HDI connectors
• CPC Class Codes: H01L 2224/73265 : Layer and wire connectors
• CPC Class Codes: H01L 2224/81 : using a bump connector
• CPC Class Codes: H01L 2224/81005 : being a temporary or sacrificial substrate
• CPC Class Codes: H01L 2224/81815 : Reflow soldering
• CPC Class Codes: H01L 2224/831 : the layer connector being supplied to the parts to be connected in the bonding apparatus
• CPC Class Codes: H01L 2224/95001 : involving a temporary auxiliary member not forming part of the bonding apparatus, e.g. removable or sacrificial coating, film or substrate
• CPC Class Codes: H01L 2224/96 : the devices being encapsulated in a common layer, e.g. neo-wafer or pseudo-wafer, said common layer being separable into individual assemblies after connecting
• CPC Class Codes: H01L 2225/06513 : Bump or bump-like direct electrical connections between devices, e.g. flip-chip connection, solder bumps
• CPC Class Codes: H01L 2225/06541 : Conductive via connections through the device, e.g. vertical interconnects, through silicon via [TSV]
• CPC Class Codes: H01L 2225/1052 : Wire or wire-like electrical connections
• CPC Class Codes: H01L 2225/1058 : Bump or bump-like electrical connections, e.g. balls, pillars, posts
• CPC Class Codes: H01L 23/3107 : the device being completely enclosed
• CPC Class Codes: H01L 23/3128 : the substrate having spherical bumps for external connection
• CPC Class Codes: H01L 24/03 : Manufacturing methods
• CPC Class Codes: H01L 24/05 : of an individual bonding area
• CPC Class Codes: H01L 24/06 : of a plurality of bonding areas
• CPC Class Codes: H01L 24/11 : Manufacturing methods for bumps on insulating substrates H01L21/4853
• CPC Class Codes: H01L 24/13 : of an individual bump connector
• CPC Class Codes: H01L 24/16 : of an individual bump connector
• CPC Class Codes: H01L 24/17 : of a plurality of bump connectors
• CPC Class Codes: H01L 24/19 : Manufacturing methods of high density interconnect preforms
• CPC Class Codes: H01L 24/20 : Structure, shape, material or disposition of high density interconnect preforms
• CPC Class Codes: H01L 24/29 : of an individual layer connector
• CPC Class Codes: H01L 24/32 : of an individual layer connector
• CPC Class Codes: H01L 24/81 : using a bump connector
• CPC Class Codes: H01L 24/82 : by forming build-up interconnects at chip-level, e.g. for high density interconnects [HDI] interconnection structure between a plurality of semiconductor chips H01L23/5389
• CPC Class Codes: H01L 24/95 : at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
• CPC Class Codes: H01L 24/96 : the devices being encapsulated in a common layer, e.g. neo-wafer or pseudo-wafer, said common layer being separable into individual assemblies after connecting
• CPC Class Codes: H01L 24/97 : the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
• CPC Class Codes: H01L 25/0657 : Stacked arrangements of devices
• CPC Class Codes: H01L 25/105 : the devices being of a type provided for in group H01L27/00
• CPC Class Codes: H01L 2924/00 : Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00012 : Relevant to the scope of the group, the symbol of which is combined with the symbol of this group
• CPC Class Codes: H01L 2924/01004 : Beryllium [Be]
• CPC Class Codes: H01L 2924/01006 : Carbon [C]
• CPC Class Codes: H01L 2924/01013 : Aluminum [Al]
• CPC Class Codes: H01L 2924/01014 : Silicon [Si]
• CPC Class Codes: H01L 2924/01028 : Nickel [Ni]
• CPC Class Codes: H01L 2924/01029 : Copper [Cu]
• CPC Class Codes: H01L 2924/01047 : Silver [Ag]
• CPC Class Codes: H01L 2924/01049 : Indium [In]
• CPC Class Codes: H01L 2924/0105 : Tin [Sn]
• CPC Class Codes: H01L 2924/01073 : Tantalum [Ta]
• CPC Class Codes: H01L 2924/01074 : Tungsten [W]
• CPC Class Codes: H01L 2924/01078 : Platinum [Pt]
• CPC Class Codes: H01L 2924/01079 : Gold [Au]
• CPC Class Codes: H01L 2924/01082 : Lead [Pb]
• CPC Class Codes: H01L 2924/01322 : Eutectic Alloys, i.e. obtained by a liquid transforming into two solid phases
• CPC Class Codes: H01L 2924/014 : Solder alloys
• CPC Class Codes: H01L 2924/0665 : Epoxy resin
• CPC Class Codes: H01L 2924/12041 : LED
• CPC Class Codes: H01L 2924/12042 : LASER
• CPC Class Codes: H01L 2924/1205 : Capacitor
• CPC Class Codes: H01L 2924/1206 : Inductor
• CPC Class Codes: H01L 2924/1207 : Resistor
• CPC Class Codes: H01L 2924/1306 : Field-effect transistor [FET]
• CPC Class Codes: H01L 2924/13091 : Metal-Oxide-Semiconductor Field-Effect Transistor [MOSFET]
• CPC Class Codes: H01L 2924/14 : Integrated circuits
• CPC Class Codes: H01L 2924/1433 : Application-specific integrated circuit [ASIC]
• CPC Class Codes: H01L 2924/14335 : Digital signal processor [DSP]
• CPC Class Codes: H01L 2924/1434 : Memory
• CPC Class Codes: H01L 2924/15311 : being a ball array, e.g. BGA
• CPC Class Codes: H01L 2924/15331 : being a ball array, e.g. BGA
• CPC Class Codes: H01L 2924/181 : Encapsulation
• CPC Class Codes: H01L 2924/3511 : Warping
• CPC Class Codes: H01L 2924/3512 : Cracking

Abstract

A semiconductor wafer has first and second opposing surfaces. A plurality of conductive vias is formed partially through the first surface of the semiconductor wafer. The semiconductor wafer is singulated into a plurality of first semiconductor die. The first semiconductor die are mounted to a carrier. A second semiconductor die is mounted to the first semiconductor die. A footprint of the second semiconductor die is larger than a footprint of the first semiconductor die. An encapsulant is deposited over the first and second semiconductor die and carrier. The carrier is removed. A portion of the second surface is removed to expose the conductive vias. An interconnect structure is formed over a surface of the first semiconductor die opposite the second semiconductor die. Alternatively, a first encapsulant is deposited over the first semiconductor die and carrier, and a second encapsulant is deposited over the second semiconductor die.

Claims

1. A method of making a semiconductor device, comprising:

providing a semiconductor wafer having first and second opposing surfaces;

forming a plurality of conductive vias partially through the first surface of the semiconductor wafer;

singulating the semiconductor wafer into a plurality of first semiconductor die;

providing a carrier;

mounting the first semiconductor die to the carrier;

mounting a second semiconductor die to the first semiconductor die;

depositing an encapsulant over the first and second semiconductor die and carrier;

removing the carrier and a portion of the second surface to expose the conductive vias; and

forming an interconnect structure over a surface of the first semiconductor die opposite the second semiconductor die.

2. The method of claim 1, wherein a footprint of the second semiconductor die is larger than a footprint of the first semiconductor die.

3. The method of claim 1, further including:

forming a conductive layer over the first surface of the substrate prior to mounting the second semiconductor die, the conductive layer being electrically connected to the conductive vias; and

forming an insulating layer over the first surface of the substrate.

4. The method of claim 1, further including depositing a mold underfill material between the first and second semiconductor die.

5. The method of claim 1, wherein the second semiconductor die includes a memory device.

6. The method of claim 1, further including stacking a plurality of second semiconductor die over the first semiconductor die.

7. A method of making a semiconductor device, comprising:

providing a plurality of first semiconductor die;

forming a plurality of conductive vias through the first semiconductor die;

providing a carrier;

mounting the first semiconductor die to the carrier;

mounting a second semiconductor die to the first semiconductor die, wherein a footprint of the second semiconductor die is larger than a footprint of the first semiconductor die; and

depositing an encapsulant over the first and second semiconductor die and carrier.

8. The method of claim 7, further including:

removing the carrier; and

forming an interconnect structure over the first semiconductor die opposite the second semiconductor die.

9. The method of claim 7, further including:

forming the plurality of conductive vias partially through a first surface of the first semiconductor die;

removing the carrier; and

removing a portion of a second surface of the first semiconductor opposite the first surface of the first semiconductor die to expose the conductive vias.

10. The method of claim 7, further including:

forming a conductive layer over the first semiconductor die prior to mounting the second semiconductor die, the conductive layer being electrically connected to the conductive vias; and

forming an insulating layer over the first semiconductor die.

11. The method of claim 7, further including depositing a mold underfill material between the first and second semiconductor die.

12. The method of claim 7, further including stacking a plurality of second semiconductor die over the first semiconductor die.

13. The method of claim 7, further including forming a plurality of conductive vias through the encapsulant.

14. A method of making a semiconductor device, comprising:

providing a plurality of first semiconductor die;

forming a plurality of conductive vias through the first semiconductor die;

providing a carrier;

mounting the first semiconductor die to the carrier;

depositing a first encapsulant over the first semiconductor die and carrier;

removing the carrier;

mounting a second semiconductor die to the first semiconductor die; and

depositing a second encapsulant over the second semiconductor die.

15. The method of claim 14, wherein a footprint of the second semiconductor die is larger than a footprint of the first semiconductor die.

16. The method of claim 14, wherein the second semiconductor die includes a memory device.

17. The method of claim 14, further including forming an interconnect structure over the first semiconductor die opposite the second semiconductor die.

18. The method of claim 14, further including:

forming the plurality of conductive vias partially through a first surface of the first semiconductor die; and

removing a portion of a second surface of the first semiconductor opposite the first surface of the first semiconductor die to expose the conductive vias.

19. The method of claim 14, further including removing a portion of the first encapsulant to expose the conductive vias.

20. The method of claim 14, further including depositing a mold underfill material between the first and second semiconductor die.

21. A semiconductor device, comprising:

a first semiconductor die having a plurality of conductive vias formed through the first semiconductor die;

a second semiconductor die mounted to the first semiconductor die, wherein a footprint of the second semiconductor die is larger than a footprint of the first semiconductor die;

an encapsulant deposited over the first and second semiconductor die; and

an interconnect structure formed over the first semiconductor die opposite the second semiconductor die.

22. The semiconductor device of claim 21, wherein the second semiconductor die includes a memory device.

23. The semiconductor device of claim 21, further including a mold underfill material deposited between the first and second semiconductor die.

24. The semiconductor device of claim 21, further including:

a conductive layer formed over the first semiconductor die and electrically connected to the conductive vias; and

an insulating layer formed over the first semiconductor die.

25. The semiconductor device of claim 21, further including a plurality of second semiconductor die stacked over the first semiconductor die.